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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGL060V5-CSG121I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 90/250闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 60K 121-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 490
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 1536
RAM 浣嶇附瑷�(j矛)锛� 18432
杓稿叆/杓稿嚭鏁�(sh霉)锛� 96
闁€鏁�(sh霉)锛� 60000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 121-VFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 121-CSP锛�6x6锛�
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IGLOO DC and Switching Characteristics
2-2
Revision 23
Table 2-2
Recommended Operating Conditions 1
Symbol
Parameter
Commercial
Industrial
Units
TA
Ambient Temperature
0 to +70
鈥�40 to +85
掳C
TJ
Junction Temperature 2
0 to +85
鈥�40 to +100
掳C
VCC3
1.5 V DC core supply voltage5
1.425 to 1.575 1.425 to 1.575
V
1.2 V鈥�1.5 V wide range DC
core supply voltage 4,6
1.14 to 1.575
V
VJTAG
JTAG DC voltage
1.4 to 3.6
V
VPUMP
Programming voltage
Programming Mode
3.15 to 3.45
V
Operation 7
0 to 3.6
V
VCCPLL8
Analog power supply (PLL)
1.5 V DC core supply voltage5
1.425 to 1.575 1.425 to 1.575
V
1.2 V 鈥� 1.5 V DC core supply
voltage4,6
1.14 to 1.575
V
VCCI and
VMV 9
1.2 V DC core supply voltage6
1.14 to 1.26
V
1.2 V DC wide range DC
supply voltage6
1.14 to 1.575
V
1.5 V DC supply voltage
1.425 to 1.575 1.425 to 1.575
V
1.8 V DC supply voltage
1.7 to 1.9
V
2.5 V DC supply voltage
2.3 to 2.7
V
3.0 V DC supply voltage 10
2.7 to 3.6
V
3.3 V DC supply voltage
3.0 to 3.6
V
LVDS differential I/O
2.375 to 2.625 2.375 to 2.625
V
LVPECL differential I/O
3.0 to 3.6
V
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi
recommends that the user follow best design practices using Microsemi鈥檚 timing and power simulation tools.
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-25 on page 2-24. VCCI should be at the same voltage within a given I/O bank.
4. All IGLOO devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using the V2
devices powered by 1.2 V supply must switch the core supply to 1.5 V for in-system programming.
5. For IGLOO V5 devices
6. For IGLOO V2 devices only, operating at VCCI
VCC.
7. VPUMP can be left floating during operation (not programming mode).
8. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter of the IGLOO FPGA Fabric User鈥檚 Guide
for further information.
9. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter of the IGLOO FPGA
Fabric User鈥檚 Guide for further information.
10. 3.3 V wide range is compliant to the JESD-8B specification and supports 3.0 V VCCI operation.
Table 2-3
Flash Programming Limits 鈥� Retention, Storage, and Operating Temperature1
Product
Grade
Programming
Cycles
Program Retention
(biased/unbiased)
Maximum Storage
Temperature TSTG (掳C) 2
Maximum Operating Junction
Temperature TJ (掳C) 2
Commercial
500
20 years
110
100
Industrial
500
20 years
110
100
Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
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