Timing Characteristics 1.5 V DC Core Voltage 1.2 V DC Core Voltage Figure 2-45 Timing D" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGL060V5-CSG121I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 53/250闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 60K 121-CSP
妯欐簴鍖呰锛� 490
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 1536
RAM 浣嶇附瑷堬細 18432
杓稿叆/杓稿嚭鏁�(sh霉)锛� 96
闁€鏁�(sh霉)锛� 60000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 121-VFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 121-CSP锛�6x6锛�
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Embedded FlashROM Characteristics
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Figure 2-45 Timing Diagram
A0
A1
tSU
tHOLD
tSU
tHOLD
tSU
tHOLD
tCKQ2
CLK
Address
Data
D0
D1
Table 2-197 Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70掳C, VCC = 1.425 V
Parameter
Description
Std.
Units
tSU
Address Setup Time
0.57
ns
tHOLD
Address Hold Time
0.00
ns
tCK2Q
Clock to Out
34.14
ns
FMAX
Maximum Clock Frequency
15
MHz
Table 2-198 Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70掳C, VCC = 1.14 V
Parameter
Description
Std.
Units
tSU
Address Setup Time
0.59
ns
tHOLD
Address Hold Time
0.00
ns
tCK2Q
Clock to Out
52.90
ns
FMAX
Maximum Clock Frequency
10
MHz
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