Revision 23 2-121 Table 2-192 RAM512X18 Commercial-Case Conditions: TJ" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGL060V5-CSG121I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 43/250闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 60K 121-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 490
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 1536
RAM 浣嶇附瑷�(j矛)锛� 18432
杓稿叆/杓稿嚭鏁�(sh霉)锛� 96
闁€(m茅n)鏁�(sh霉)锛� 60000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 121-VFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 121-CSP锛�6x6锛�
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IGLOO Low Power Flash FPGAs
Revision 23
2-121
Table 2-192 RAM512X18
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tAS
Address setup time
0.83
ns
tAH
Address hold time
0.16
ns
tENS
REN, WEN setup time
0.73
ns
tENH
REN, WEN hold time
0.08
ns
tDS
Input data (WD) setup time
0.71
ns
tDH
Input data (WD) hold time
0.36
ns
tCKQ1
Clock High to new data valid on RD (output retained)
4.21
ns
tCKQ2
Clock High to new data valid on RD (pipelined)
1.71
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same address -
Applicable to Opening Edge
0.35
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same address -
Applicable to Opening Edge
0.42
ns
tRSTBQ
RESET Low to data out Low on RD (flow-through)
2.06
ns
RESET Low to data out Low on RD (pipelined)
2.06
ns
tREMRSTB
RESET removal
0.61
ns
tRECRSTB
RESET recovery
3.21
ns
tMPWRSTB RESET minimum pulse width
0.68
ns
tCYC
Clock cycle time
6.24
ns
FMAX
Maximum frequency
160 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
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