參數(shù)資料
型號(hào): ADV7391BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 6/108頁(yè)
文件大?。?/td> 0K
描述: IC ENCODER VIDEO W/DAC 32LFCSP
產(chǎn)品變化通告: ADV734x, ADV739x Feature Improvement
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編碼器
應(yīng)用: 機(jī)頂盒,視頻播放器,顯示器
電壓 - 電源,模擬: 2.6 V ~ 3.46 V
電壓 - 電源,數(shù)字: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 托盤
配用: EVAL-ADV7391EBZ-ND - BOARD EVAL FOR ADV7391 ENCODER
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 103 of 108
Table 126. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 127. 10-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x6C
10-bit input enabled.
Table 128. 8-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 129. 10-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x6C
10-bit input enabled.
Table 130. 8-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 131. 10-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x6C
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x6C
10-bit input enabled.
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