參數(shù)資料
型號: ADV7391BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 48/108頁
文件大小: 0K
描述: IC ENCODER VIDEO W/DAC 32LFCSP
產(chǎn)品變化通告: ADV734x, ADV739x Feature Improvement
標準包裝: 1
類型: 視頻編碼器
應(yīng)用: 機頂盒,視頻播放器,顯示器
電壓 - 電源,模擬: 2.6 V ~ 3.46 V
電壓 - 電源,數(shù)字: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 托盤
配用: EVAL-ADV7391EBZ-ND - BOARD EVAL FOR ADV7391 ENCODER
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 44 of 108
SR7 to
Bit Number1
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0xBB
Field count
x
Read only
0x0X
Reserved
0
Reserved
Encoder version code
0
Read only; first
encoder version2
0
1
Read only; second
encoder version
1
x = Logic 0 or Logic 1.
2
See the HD Interlace External HSYNC and VSYNC Considerations section for information about the first encoder version.
Table 33. Register 0xC9 to Register 0xCE
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0xC9
Teletext control
Teletext enable
0
Disabled.
0x00
1
Enabled.
Teletext request mode
0
Line request signal.
1
Bit request signal.
Teletext input pin
select1
0
VSYNC.
1
P0.
Reserved
0
Reserved.
0xCA
Teletext request
control
Teletext request falling
edge position control
0
0 clock cycles.
0x00
0
1
One clock cycle.
1
0
14 clock cycles.
1
15 clock cycles.
Teletext request rising
edge position control
0
0 clock cycles.
0
1
One clock cycle.
1
0
14 clock cycles.
1
15 clock cycles.
0xCB
TTX Line Enable 0
Teletext on odd fields
22
21
20
19
18
17
16
15
Setting any of these bits
to 1 enables teletext on
the line number indicated
by the bit settings.
0x00
0xCC
TTX Line Enable 1
Teletext on odd fields
14
13
12
11
10
9
8
7
0x00
0xCD
TTX Line Enable 2
Teletext on even fields
22
21
20
19
18
17
16
15
0x00
0xCE
TTX Line Enable 3
Teletext on even fields
14
13
12
11
10
9
8
7
0x00
1
The use of P0 as the teletext input pin is available on the ADV7392/ADV7393 (40-pin devices) only.
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