參數(shù)資料
型號： ADV7391BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 30/108頁
文件大?。?/td> 0K
描述： IC ENCODER VIDEO W/DAC 32LFCSP
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
標準包裝： 1
類型： 視頻編碼器
應(yīng)用： 機頂盒，視頻播放器，顯示器
電壓 - 電源，模擬： 2.6 V ~ 3.46 V
電壓 - 電源，數(shù)字： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤
配用： EVAL-ADV7391EBZ-ND - BOARD EVAL FOR ADV7391 ENCODER
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 28 of 108
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV739x via the MPU port, except for registers that are
specified as read-only or write-only registers.
The subaddress register determines the register accessed by the
next read or write operation. All communication through the
MPU port starts with an access to the subaddress register. A
read/write operation is then performed from/to the target
address, incrementing to the next address until the transaction
is complete.
REGISTER PROGRAMMING
Table 17 to Table 34 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines which
register performs the next operation.
Table 17. Register 0x00
SR7 to
Bit Number
Register
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Setting
Value
0x00
Power
mode
Sleep mode. With this control enabled, the current consumption is
reduced to A level. All DACs and the internal PLL circuit are
disabled. Registers can be read from and written to in sleep mode.
0
Sleep
mode off
0x12
1
Sleep
mode on
PLL and oversampling control. This control allows the internal PLL
circuit to be powered down and the oversampling to be switched off.
0
PLL on
1
PLL off
DAC 3: power on/off.
0
DAC 3 off
1
DAC 3 on
DAC 2: power on/off.
0
DAC 2 off
1
DAC 2 on
DAC 1: power on/off.
0
DAC 1 off
1
DAC 1 on
Reserved.
0
Table 18. Register 0x01 to Register 0x09
SR7 to
Bit Number1
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0x01
Mode
select
Reserved.
0
0x00
DDR clock edge alignment
(used only for ED2 and HD
DDR modes)
0
Chroma clocked in on rising clock edge and
luma clocked in on falling clock edge.
0
1
Reserved.
1
0
Reserved.
1
Luma clocked in on rising clock edge and
chroma clocked in on falling clock edge.
Reserved
0
Input mode
(see Subaddress 0x30, Bits[7:3]
for ED/HD standard selection)
0
SD input.
0
1
ED/HD-SDR input.3
0
1
0
ED/HD-DDR input.
0
1
Reserved.
1
0
Reserved.
1
0
1
Reserved.
1
0
Reserved.
1
ED (at 54 MHz) input.
Reserved
0
相關(guān)PDF資料
PDF描述
ADV7511KSTZ IC XMITTER HDMI 12BIT 100LQFP
ADV7511WBSWZ IC XMITTER HDMI AUTO 64LQFP
ADV7622BSTZ-RL IC TXRX HDMI 4:1 144LQFP
ADV7623BSTZ IC TXRX HDMI 4:1 144LQFP
ADW54010Z-0REEL IC SWITCH DUAL SPDT 10MSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7391BCPZ-REEL 功能描述:IC VIDEO ENCODER SD/HD 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7391EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7391WBCPZ 制造商:Analog Devices 功能描述:
ADV7391WBCPZ-RL 制造商:Analog Devices 功能描述:
ADV7392 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*