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參數(shù)資料
| 型號： | ADV7324KSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 25/92頁 |
| 文件大?。?/td> | 992K |
| 代理商： | ADV7324KSTZ |
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ADV7324
REGISTER ACCESS
The MPU can write to or read from all registers of the
ADV7324 except the subaddress registers, which are write only
registers. The subaddress register selected determines which
register the next read or write operation will access. All
communication with the part through the bus starts with an
access to the subaddress register. A read/write operation is then
performed from/to the target address, which increments to the
next address until a stop command is performed on the bus.
Rev. 0 | Page 25 of 92
REGISTER PROGRAMMING
The following tables describe the functionality of each register. All
registers can be read from and written to, unless otherwise stated.
SUBADDRESS REGISTERS (SR7 TO SR0)
Each subaddress register is an 8-bit, write only register. After the
encoder’s bus is accessed and a read or write operation is selected,
the subaddress is set up. The subaddress register determines to
or from which register the operation takes place.
Table 7. Registers 0x00 to 0x01
SR7–
SR0
Register
0x00
Mode
Register
Bit Description
Sleep Mode. With this
control enabled, the
current consumption is
reduced to μA level. All
DACs and the internal
PLL cct are disabled. I
2
C
registers can be read from
and written to in sleep
mode.
PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the oversampling to be
switched off.
DAC F: Power On/Off.
DAC E: Power On/Off.
DAC D: Power On/Off.
DAC C: Power On/Off.
DAC B: Power On/Off.
DAC A: Power On/Off.
Reserved.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
Register Setting
Sleep mode off.
Sleep mode on.
Reset Value
(Shaded)
0xFC
Power
0
1
PLL on.
PLL off.
0x01
Mode
Select
Register
0
1
0
1
0
1
0
1
0
1
0
1
0
DAC F off.
DAC F on.
DAC E off.
DAC E on.
DAC D off.
DAC D on.
DAC C off.
DAC C on.
DAC B off.
DAC B on.
DAC A off.
DAC A on.
Reserved.
Clock Edge.
0
Cb clocked upon rising
edge.
Y clocked upon rising
edge.
Must be set if the phase
delay between the two
input clocks is <9.25 ns
or >27.75 ns.
SD input only.
PS input only.
HDTV input only.
SD and PS (20-bit).
SD and PS (10-bit).
SD and HDTV
(SD oversampled).
SD and HDTV
(HDTV oversampled).
PS only (at 54 MHz).
Allows data to be
applied to data ports in
various configurations
(SD feature only).
1
Only for PS
interleaved
input at 27 MHz.
Reserved.
Clock Align.
0
1
0
Only if two
input clocks are
used.
Input Mode.
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0x38
1
1
0
Y/C/S Bus Swap.
0
1
1
1
See Table 21.
1
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