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參數(shù)資料
| 型號： | ADV7324KSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 23/92頁 |
| 文件大?。?/td> | 992K |
| 代理商： | ADV7324KSTZ |
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ADV7324
MPU PORT DESCRIPTION
The ADV7324 supports a 2-wire serial (I
2
C-compatible)
microprocessor bus driving multiple peripherals. This port
operates in an open-drain configuration. Two inputs, serial data
(SDA) and serial clock (SCL), carry information between any
device connected to the bus and the ADV7324. Each slave
device is recognized by a unique address. The ADV7324 has
four possible slave addresses for both read and write operations.
These are unique addresses for each device and are illustrated in
Figure 44. The LSB sets either a read or write operation. Logic 1
corresponds to a read operation, while Logic 0 corresponds to a
write operation. A1 is enabled by setting the ALSB pin of the
ADV7324 to Logic 0 or Logic 1. When ALSB is set to 1, there is
greater input bandwidth on the I
2
C lines, which allows high
speed data transfers on this bus. When ALSB is set to 0, there is
reduced input bandwidth on the I
2
C lines, which means that
pulses of less than 50 ns will not pass into the I
2
C internal
controller. This mode is recommended for noisy systems.
Rev. 0 | Page 23 of 92
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
ALSB PIN
READ/WRITE
CONTROL
0 WRITE
1 READ
0
Figure 44. ADV7324 Slave Address = 0xD4
To control the various devices on the bus, the following
protocol must be followed. First, the master initiates a data
transfer by establishing a start condition, defined by a high-to-
low transition on SDA while SCL remains high. This indicates
that an address/data stream will follow. All peripherals respond
to the start condition and shift the next eight bits (7-bit address
+ R/W bit). The bits are transferred from MSB down to LSB.
The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This is known as an acknowledge bit. All other devices
withdraw from the bus at this point and maintain an idle
condition. The idle condition is where the device monitors the
SDA and SCL lines, waiting for the start condition and the
correct transmitted address. The R/W bit determines the
direction of the data.
Logic 0 on the LSB of the first byte means that the master will
write information to the peripheral. Logic 1 on the LSB of the
first byte means that the master will read information from the
peripheral.
The ADV7324 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
address plus the R/W bit. It interprets the first byte as the device
address and the second byte as the starting subaddress. There is
a subaddress auto-increment facility. This allows data to be
written to or read from registers in ascending subaddress
sequence, starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
updating all of the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause the
device to immediately jump to the idle condition. During a
given SCL high period, the user should only issue a start
condition, a stop condition, or a stop condition followed by a
start condition. If an invalid subaddress is issued by the user,
the ADV7324 does not issue an acknowledge and returns to the
idle condition. If the user utilizes the auto-increment method of
addressing the encoder and exceeds the highest subaddress, the
following actions are taken:
In read mode, the highest subaddress register contents are
output until the master device issues a no acknowledge. This
indicates the end of a read. A no acknowledge condition is
when the SDA line is not pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded into
any subaddress register, a no acknowledge is issued by the
ADV7324, and the part returns to the idle condition.
Before writing to the subcarrier frequency registers, it is required
to reset ADV7324 at least once after power-up.
The four subcarrier frequency registers must be updated,
starting with Subcarrier Frequency Register 0 and ending with
Subcarrier Frequency Register 3. The subcarrier frequency will
only update after the last subcarrier frequency register byte has
been received by the ADV7324.
Figure 45 illustrates an example of data transfer for a write
sequence and the start and stop conditions. Figure 46 shows bus
write and read sequences.
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