參數(shù)資料
型號(hào)： ADV7322
廠商： Analog Devices, Inc.
英文描述： Multiformat 11-Bit HDTV Video Encoder
中文描述： 多格式11位高清晰度電視視頻編碼器
文件頁數(shù)： 72/88頁
文件大?。?/td> 991K
代理商： ADV7322
ADV7322
Preliminary Technical Data
The register settings in Table 39 are used to generate an SD
NTSC CVBS output on DAC A, S-video on DACs B and C, and
YPrPb on DACs D, E, and F. Upon power-up, the subcarrier
registers are programmed with the appropriate values for NTSC.
All other registers are set as normal/default.
Table 39. NTSC Test Pattern Register Writes
Subaddress
Register Setting
0x00
0xFC
0x40
0x10
0x42
0x40
0x44
0x40 (internal test pattern on)
0x4A
0x08
Rev. PrA | Page 72 of 88
For PAL CVBS output on DAC A, the same settings are used,
except that Subaddress 0x40 is programmed to 0x11 and the Fsc
registers are programmed as shown in Table 40.
Table 40. PAL Fsc Register Writes
Subaddress
Description
0x4C
Fsc0
0x4D
Fsc1
0x4E
Fsc2
0x4F
Fsc3
Register Setting
0xCB
0x8A
0x09
0x2A
Note that when programming the Fsc registers, the user must
write the values in the sequence Fsc0, Fsc1, Fsc2, Fsc3. The full
Fsc value to be written is only accepted after the Fsc3 write is
complete.
The register settings in Table 41 are used to generate a 525p
hatch pattern on DAC D, E, and F. All other registers are set as
normal/default.
Table 41. 525p Test Pattern Register Writes.
Subaddress
Ox00
0x01
0x10
0x11
0x16
0x17
0x18
Register Setting
0xFC
0x10
0x00
0x05
0xA0
0x80
0x80
For 625p hatch pattern on DAC D, the same register settings are
used except that Subaddress 0x10 = 0x18.
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