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參數(shù)資料
| 型號： | ADV7322 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 11-Bit HDTV Video Encoder |
| 中文描述： | 多格式11位高清晰度電視視頻編碼器 |
| 文件頁數(shù)： | 27/88頁 |
| 文件大?。?/td> | 991K |
| 代理商： | ADV7322 |
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Preliminary Technical Data
ADV7322
Table 8. Registers 0x02 to 0x0F
SR7–
SR0
Register
0x02
Mode Register 0
Rev. PrA | Page 27 of 88
Bit Description
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
Bit 0
0
Register Setting
Zero must be written to
these bits.
Disabled.
Enabled.
Disable manual RGB matrix
adjust.
Enable manual RGB matrix
adjust.
No sync.
Sync on all RGB outputs.
RGB component outputs.
YPrPb component outputs.
No Sync output.
Output SD syncs on
S_HSYNC, S_VSYNC,
S_BLANK pins.
No sync output.
Output HD,ED, syncs on
S_HSYNC, S_VSYNC.
LSB for GY.
LSB for RV.
LSB for BU.
LSB for GV.
LSB for GU.
Bits 9–2 for GY.
Bits 9–2 for GU.
Bits 9–2 for GV.
Bits 9–2 for BU.
Bits 9–2 for RV.
0%
Reset Values
0x20
0
0
1
Test Pattern Black
Bar
Manual RGB
Matrix Adjust
0x11, Bit 2 must
also be enabled.
1
0
1
0
1
0
1
Sync on RGB
1
RGB/YPrPb
Output
SD Sync
0
1
HD Sync
0x03
0x04
RGB Matrix 0
RGB Matrix 1
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
0
0x03
0xF0
0x4E
0x0E
0x24
0x92
0x7C
0x00
0x05
0x06
0x07
0x08
0x09
0x0A
RGB Matrix 2
RGB Matrix 3
RGB Matrix 4
RGB Matrix 5
RGB Matrix 6
DAC A, B, C Output
Level
2
Positive Gain to
DAC Output
Voltage
Negative Gain to
DAC Output
Voltage
Positive Gain to
DAC Output
Voltage
Negative Gain to
DAC Output
Voltage
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
…
1
0
0
+0.018%
0.036%
…
+7.382%
+7.5%
7.5%
0x0B
DAC D, E, F Output
Level
1
1
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
1
0
…
1
0
7.382%
7.364%
…
0.018%
0%
0x00
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
…
1
0
0
+0.018%
0.036%
…
+7.382%
+7.5%
7.5%
0x0C
0x0D
0x0E
0x0F
1
1
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
1
0
…
1
7.382%
7.364%
…
0.018%
0x00
0x00
0x00
0x00
1
For more detail, refer to Appendix 7.
2
For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.
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