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參數(shù)資料
| 型號： | ADV7322 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 11-Bit HDTV Video Encoder |
| 中文描述： | 多格式11位高清晰度電視視頻編碼器 |
| 文件頁數(shù)： | 40/88頁 |
| 文件大?。?/td> | 991K |
| 代理商： | ADV7322 |
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ADV7322
Preliminary Technical Data
Rev. PrA | Page 40 of 88
CLKIN_A
CLKIN_B
MPEG2
DECODER
3
27MHz
8
YCrCb
INTERLACED TO
PROGRESSIVE
8
CrCb
8
Y
3
27MHz
S[7:0]
C[7:0]
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
ADV7322
0
S_VSYNC,
S_HSYNC,
S_BLANK
Figure 50. Simultaneous PS and SD Input
CLKIN_A
CLKIN_B
SDTV
DECODER
3
27MHz
8
YCrCb
8
CrCb
8
Y
3
74.25MHz
1080i
OR
720p
OR
1035i
S[7:0]
C[7:0]
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
ADV7322
HDTV
DECODER
0
S_VSYNC,
S_HSYNC,
S_BLANK
Figure 51. Simultaneous HD and SD Input
If in simultaneous SD/HD input mode and the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK
ALIGN bit [Address 0x01, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.
CLKIN_A
CLKIN_B
0
t
DELAY
<
9.25ns OR
t
DELAY
>
27.75ns
Figure 52. Clock Phase with Two Input Clocks
PROGRESSIVE SCAN AT 27 MHZ (DUAL EDGE)
OR 54 MHZ
Address[0x01]: Input Mode 100 or 111, Respectively
YCrCb progressive scan data can be input at 27 MHz or
54 MHz. The input data is interleaved onto a single 8-bit bus
and is input on Pins Y7 to Y0. When a 27 MHz clock is supplied,
the data is clocked in on the rising and falling edge of the input
clock and CLOCK EDGE [Address 0x01, Bit 1] must be set
accordingly.
Table 22 provides an overview of all possible input configurations.
Figure 53, Figure 54, and Figure 55 show the possible conditions:
(a) Cb data on the rising edge; and (b) Y data on the rising edge.
FF
00
00
XY
Y0
Y1
Cr0
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
Y7–Y0
Cb0
0
Figure 53. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
FF
00
00
XY
Cb0
Cr0
Y1
CLKIN_B
Y7–Y0
Y0
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
0
Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
PIXEL INPUT
DATA
FF
00
00
XY
Cb0
Y0
Y1
Cr0
CLKIN_B
WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
0
Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
MPEG2
DECODER
CLKIN_A
Y[7:0]
INTERLACED
TO
PROGRESSIVE
YCrCb
8
3
27MHz OR 54MHz
YCrCb
ADV7322
P_VSYNC,
P_HSYNC,
P_BLANK
0
Figure 56. 10-Bit PS at 27 MHz or 54 MHz
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