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參數(shù)資料
| 型號： | ADV7314KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 38/84頁 |
| 文件大?。?/td> | 1069K |
| 代理商： | ADV7314KST |
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REV. 0
–38–
ADV7314
Reset Sequence
A reset is activated with a high-to-low transition on the
RESET
pin
[Pin 33] according to the timing specifications. The ADV7314
will revert to the default output configuration. Figure 32 illus-
trates the
RESET
sequence timing.
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW Sync control bit can be used for non-
standard input video, i.e., in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/field are reached. In rewind mode, this sync
signal usually occurs after the total number of lines/field are
reached. Conventionally this means that the output video will
have corrupted field signals, one generated by the incoming
video and one when the internal lines/field counters reach the
end of a field.
When the VCR FF/RW sync control is enabled [Subaddress 42h,
Bit 5] the lines/field counters are updated according to the
incoming
VSYNC
signal and the analog output matches the
incoming
VSYNC
signal.
This control is available in all slave timing modes except Slave
Mode 0.
LCC1
GLL
P19–P10
ADV7183A
VIDEO
DECODER
COMPOSITE
VIDEO
e.g., VCR
OR CABLE
CLKIN_A
RTC_SCR_TR
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
Y9-Y0/S9–S0
*
RTC
LOW
COUNT START
128
TIME SLOT 01
13
0
14 BITS
SUBCARRIER
PHASE
14
21
19
F
SC
PLL INCREMENT
1
VALID
SAMPLE
INVALID
SAMPLE
8/LINE
LOCKED
CLOCK
6768
4 BITS
RESERVED
0
SEQUENCE
BIT
2
RESET
BIT
3
RESERVED
5 BITS
RESERVED
ADV7314
NOTES
F
SC
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7314 F
SC
DDS REGISTER IS F
SC
PLL INCREMENTS BITS 21:0
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7314.
2
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE
3
SEQUENCE BIT
RESET ADV7314 DDS
*
SELECTED BY REGISTER
ADDRESS 01h BIT 7
Figure 31. RTC Timing and Connections
XXXXXX
XXXXXX
OFF
DIGITAL TIMING SIGNALS SUPPRESSED
VALID VIDEO
TIMING ACTIVE
RESET
DIGITAL TIMING
DACs
A, B, C
PIXEL DATA
VALID
Figure 32.
RESET
Timing Sequence
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