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參數(shù)資料
| 型號： | ADV7314KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 17/84頁 |
| 文件大?。?/td> | 1069K |
| 代理商： | ADV7314KST |
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REV. 0
ADV7314
–17–
MPU PORT DESCRIPTION
The ADV7314 supports a 2-wire serial (I
2
C compatible) micro-
processor bus driving multiple peripherals. Two inputs, serial
data (SDA) and serial clock (SCL), carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7314 has four possible slave
addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 17. The
LSB sets either a read or write operation. Logic 1 corresponds
to a read operation, while Logic 0 corresponds to a write opera-
tion. A1 is set by setting the ALSB pin of the ADV7314 to
Logic 0 or Logic 1. When ALSB is set to 1, there is greater
input bandwidth on the I
2
C lines, which allows high speed data
transfers on this bus. When ALSB is set to 0, there is reduced
input bandwidth on the I
2
C lines, which means that pulses of
less than 50 ns will not pass into the I
2
C internal controller.
This mode is recommended for noisy systems.
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0 WRITE
1 READ
Figure 17. ADV7314 Slave Address = D4h
To control the various devices on the bus, the following protocol
must be followed. First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA, while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start
condition and shift the next eight bits (7-bit address + R/
W
bit).
The bits are transferred from MSB down to LSB. The periph-
eral that recognizes the transmitted address responds by pulling
the data line low during the ninth clock pulse. This is known as
an acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
when the device monitors the SDA and SCL lines waiting for
the start condition and the correct transmitted address. The
R/
W
bit determines the direction of the data.
A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7314 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits wide, supporting the 7-bit
addresses plus the R/
W
bit. It interprets the first byte as the
device address and the second byte as the starting subaddress.
There is a subaddress auto-increment facility, which allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
having to update all the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then these cause an
immediate jump to the idle condition. During a given SCL high
period, the user should issue only one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7314 will not issue an acknowledge and will return to the
idle condition. If in auto-increment mode the user exceeds the
highest subaddress, the following action will be taken:
1. In read mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is when the SDA line is not
pulled low on the ninth pulse.
2. In write mode, the data for the invalid byte will not be loaded
into any subaddress register, a no-acknowledge will be issued
by the ADV7314, and the part will return to the idle condition.
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