參數(shù)資料
型號(hào)： ADV7314
廠商： Analog Devices, Inc.
英文描述： Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
中文描述： 多格式視頻編碼器216兆赫六噪聲整形的14位DAC
文件頁(yè)數(shù)： 37/84頁(yè)
文件大?。?/td> 1069K
代理商： ADV7314
REV. 0
ADV7314
–37–
SD Real-Time Control, Subcarrier Reset, and Timing Reset
[Subaddress 44h, Bit 2,1]
Together with the RTC_SCR_TR pin and SD Mode Register 3,
the ADV7314 can be used in timing reset mode, subcarrier phase
reset mode, or RTC mode.
Timing Reset Mode
A timing reset is achieved in a low-to-high transition on the
RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set to
low), the internal counters will commence counting again, the
field count will start on Field 1, and the subcarrier phase will
be reset.
The minimum time the pin has to be held high is one clock
cycle; otherwise this reset signal might not be recognized.
This timing reset applies to the SD timing counters only.
Subcarrier Phase Reset
A low-to-high transition on the RTC_SCR_TR pin (Pin 31) will
reset the subcarrier phase to zero on the field following the
subcarrier phase reset when the SD RTC/TR/SCR control bits
at Address 44h are set to 01.
This reset signal will have to be held high for a minimum of one
clock cycle.
Since the field counter is not reset, it is recommended that the
reset signal should be applied in Field 7 [PAL] or Field 3
[NTSC]. The reset of the phase will then occur on the next
field, i.e., Field 1, being lined up correctly with the internal
counters. The field count register at Address 7Bh can be used to
identify the number of the active field.
RTC Mode
In RTC mode, the ADV7314 can be used to lock to an external
video source. The real-time control mode allows the ADV7314
to automatically alter the subcarrier frequency to compensate
for line length variations. When the part is connected to a device
that outputs a digital datastream in the RTC format (such as an
ADV7183A video decoder, see Figure 31), the part will auto-
matically change to the compensated subcarrier frequency on a
line by line basis. This digital datastream is 67 bits wide and the
subcarrier is contained in Bits 0 to 21. Each bit is two clock
cycles long. 00h should be written into all four subcarrier
frequency registers when using this mode.
DISPLAY
NO TIMING RESET APPLIED
TIMING RESET APPLIED
START OF FIELD 4 OR 8
F
SC
PHASE = FIELD 4 OR 8
F
SC
PHASE = FIELD 1
TIMING RESET PULSE
307
310
307
1
2
3
4
5
6
7
21
313
320
DISPLAY
START OF FIELD 1
Figure 29. Timing Reset Timing Diagram
NO F
SC
RESET APPLIED
F
SC
PHASE = FIELD 4 OR 8
307
310
313
320
DISPLAY
START OF FIELD 4 OR 8
F
SC
RESET APPLIED
F
SC
RESET PULSE
F
SC
PHASE = FIELD 1
307
310
313
320
DISPLAY
START OF FIELD 4 OR 8
Figure 30. Subcarrier Reset Timing Diagram
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