參數(shù)資料
型號(hào)： ADV7314
廠商： Analog Devices, Inc.
英文描述： Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
中文描述： 多格式視頻編碼器216兆赫六噪聲整形的14位DAC
文件頁(yè)數(shù)： 27/84頁(yè)
文件大?。?/td> 1069K
代理商： ADV7314
REV. 0
ADV7314
–27–
SR7-
SR0
4Ah
Register
SD Timing Register 0
Bit Description
SD Slave/Master Mode
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0 Register Setting
0
Slave mode
1
Master mode
Mode 0
Mode 1
Mode 2
Mode 3
Enabled
Disabled
No delay
2 clk cycles
4 clk cycles
6 clk cycles
–40 IRE
–7.5 IRE
0
A low-high-low transistion will
reset the internal SD timing
counters
Reset
Value
08h
SD Timing Mode
0
0
1
1
0
1
0
1
SD
BLANK
Input
0
1
SD Luma Delay
0
0
1
1
0
1
0
1
SD Min. Luma Value
0
1
0
SD Timing Reset
x
0
0
0
0
0
4Bh
SD Timing Register 1
SD
HSYN
C Width
0
0
1
1
0
1
0
1
Ta = 1 clk cycle
Ta = 4 clk cycles
Ta = 16 clk cycles
Ta = 128 clk cycles
Tb = 0 clk cycle
Tb = 4 clk cycles
Tb = 8 clk cycles
Tb = 18 clk cycles
Tc = Tb
Tc = Tb + 32 s
1 clk cycle
4 clk cycles
16 clk cycles
128 clk cycles
0 clk cycles
1 clk cycle
2 clk cycles
3 clk cycles
Subcarrier Frequency Bit 7–0
Subcarrier Frequency Bit 15–8
Subcarrier Frequency Bit 23–16
Subcarrier Frequency Bit 31–24
Subcarrier Phase Bit 9–2
Extended Data Bit 7–0
00h
SD
HSYNC
to
VSYNC
delay
0
0
1
1
0
1
0
1
x
x
0
0
1
1
0
1
0
1
0
1
0
0
1
1
x
x
x
x
x
x
0
1
0
1
x
x
x
x
x
x
4Ch
4Dh
4Eh
4Fh
50h
51h
SD F
SC
Register 0
SD F
SC
Register 1
SD F
SC
Register 2
SD F
SC
Register 3
SD F
SC
Phase
SD Closed Captioning
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16h
7Ch
F0h
21h
00h
00h
Extended Data on Even
Fields
Extended Data on Even
Fields
Data on Odd Fields
Data on Odd Fields
Pedestal on Odd Fields
Pedestal on Odd Fields
Pedestal on Even Fields 17
Pedestal on Even Fields 25
52h
SD Closed Captioning
x
x
x
x
x
x
x
x
Extended Data Bit 15–8
00h
53h
54h
55h
56h
57h
58h
SD Closed Captioning
SD Closed Captioning
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
x
x
17
25
x
x
16
24
16
24
x
x
15
23
15
23
x
x
14
22
14
22
x
x
13
21
13
21
x
x
12
20
12
20
x
x
11
19
11
19
x
x
10
18
10
18
Data Bit 7–0
Data Bit 15–8
Setting any of these bits to 1 will
disable pedestal on the line
number indicated by the bit
settings.
00h
00h
00h
00h
00h
00h
SD
HSYNC
to
VSYNC
Rising
Edge Delay [Mode 1
only]
VSYNC
Width
[Mode 2 only]
HSYNC
to Pixel Data
Adjust
LINE 313
LINE 314
LINE 1
t
B
HSYNC
VSYNC
t
A
t
C
Figure 20. Timing Register 1 in PAL Mode
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