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    參數(shù)資料
    型號: ADV7302A
    廠商: Analog Devices, Inc.
    英文描述: 32X2 SHROUDED VERT. HDR
    中文描述: 多格式統(tǒng)計,逐行掃描/ HDTV視頻編碼器與六11位DAC
    文件頁數(shù): 33/68頁
    文件大?。?/td> 1177K
    代理商: ADV7302A
    REV. A
    ADV7302A/ADV7303A
    –33–
    TIMING MODES
    HD Async Timing Mode
    [Subaddress 10h, Bits 3–2]
    For any input data that does not conform to SMPTE293M,
    SMPTE274M, SMPTE296M, or ITU-R.BT1358 standards,
    an Asynchronous Timing Mode can be used to interface to the
    ADV7302A/ADV7303A. Timing control signals for HSYNC,
    VSYNC, and BLANK have to be programmed by the user.
    Macrovision is not available in Async Timing Mode.
    Figure 28 shows an example of how to program the ADV7302A/
    ADV7303A to accept a different high definition standard other
    than SMPTE293M, SMPTE274M, SMPTE296M, or
    ITU-R.BT1358 standards.
    Table XIV must be followed when programming the control sig-
    nals in Async Timing Mode.
    HD Timing Reset
    A timing reset is achieved in setting the HD Timing Reset Con-
    trol Bit at Address 14h from “0” to “1.” In this state, the
    horizontal and vertical counters will remain reset. On setting
    this bit back to “0,” the internal counters will again commence
    counting. The minimum time the pin has to be held high is one
    clock cycle; otherwise, this reset signal might not be recognized.
    This timing reset applies to the HD timing counters only.
    SD Timing
    Real-time Control, Subcarrier Reset, Timing Reset
    [Subaddress 44h, Bits 2–1]
    Together with the RTC_SCR_TR Pin and SD Mode Register 3
    [Address 44h, Bits 1–2] the ADV7302A/ADV7303A can be
    used in Timing Reset Mode, Subcarrier Phase Reset Mode,
    or RTC Mode.
    a. A timing reset is achieved in a low-to-high transition on the
    RTC_SCR_TR Pin (Pin 31). In this state, the horizontal and
    vertical counters will remain reset. On releasing this pin (set
    to low), the internal counters will again commence counting.
    The minimum time the pin has to be held high is one clock
    cycle; otherwise, this reset signal might not be recognized. This
    timing reset applies to the SD timing counters only.
    b. Subcarrier phase reset, a low-to-high transition on the
    RTC_SCR_TR pin (Pin 31), will reset the subcarrier phase
    to zero when the SD RTC/TR/SCR control bits at Address 44h
    are set to “01.” This reset signal will have to be held high for
    a minimum of one clock cycle. Since the Field Counter is
    not reset, it is recommended to apply the reset in Field 7
    (PAL). The reset of the phase will then occur on the next field
    by being correctly lined up with the internal counters. The
    Field Count Register at Address 7Bh can be used to identify
    the number of the active field.
    c. In RTC Mode, the ADV7302A/ADV7303A can be used to
    lock to an external video source. The Real-time Control Mode
    allows the ADV7302A/ADV7303A to automatically alter the
    subcarrier frequency to compensate for line length variations.
    When the part is connected to a device that outputs a digital
    data stream in the RTC format (such as a ADV7185 video
    decoder, see Figure 29), the part will automatically change to
    the compensated subcarrier frequency on a line-by-line basis.
    This digital data stream is 67 bits wide and the subcarrier is
    contained in Bits 0 to 21. Each bit is two clock cycles long.
    00h should be written into all four Subcarrier Frequency
    Registers when using this mode.
    CLK
    ACTIVE VIDEO
    PROGRAMMABLE
    INPUT TIMING
    ANALOG
    OUTPUT
    a
    b
    c
    d
    81
    66
    66
    243
    1920
    HORIZONTAL SYNC
    e
    P_HSYNC
    P_VSYNC
    P_BLANK
    *
    *
    SET ADDRESS 10h, BIT 6 TO “1”
    Figure 28. Async Timing Mode, Programming Input Control Signals for SMPTE295M Compatibility
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