參數(shù)資料
型號(hào)： ADV7302A
廠商： Analog Devices, Inc.
英文描述： 32X2 SHROUDED VERT. HDR
中文描述： 多格式統(tǒng)計(jì)，逐行掃描/ HDTV視頻編碼器與六11位DAC
文件頁(yè)數(shù)： 14/68頁(yè)
文件大?。?/td> 1177K
代理商： ADV7302A
REV. A
–14–
ADV7302A/ADV7303A
MPU PORT DESCRIPTION
The ADV7302A/ADV7303A supports a 2-wire serial (I
2
C com-
patible) microprocessor bus driving multiple peripherals. Two
inputs, Serial Data (SDA) and Serial Clock (SCL), carry infor-
mation between any device connected to the bus. Each slave
device is recognized by a unique address. The ADV7302A/
ADV7303A has four possible slave addresses for both read and
write operations. These are unique addresses for each device and
are illustrated in Figures 15 and 16. The LSB sets either a read or
write operation. Logic Level “1” corresponds to a read operation,
while Logic Level “0” corresponds to a write operation. A1 is set
by setting the ALSB Pin of the ADV7302A/ADV7303A to Logic
Level “0” or Logic Level “1.” When ALSB is set to “1,” there is
greater input bandwidth on the I
2
C lines, which allows high
speed data transfers on this bus. When ALSB is set to “0,” there
is reduced input bandwidth on the I
2
C lines, which means that
pulses of less than 50 ns will not pass into the I
2
C internal con-
troller. This mode is recommended for noisy systems.
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0 WRITE
1 READ
Figure 15. ADV7302A Slave Address = D4h
0
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0 WRITE
1 READ
Figure 16. ADV7303A Slave Address = 54h
To control the various devices on the bus, the following protocol
must be followed. First, the master initiates a data transfer by estab-
lishing a start condition, defined by a high-to-low transition on
SDA, while SCLK remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start condition
and shift the next eight bits (7-bit address + R/
W
Bit). The bits
are transferred from MSB down to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
Acknowledge Bit. All other devices withdraw from the bus at this
point and maintain an idle condition. The idle condition is where
the device monitors the SDA and SCLK lines waiting for the
start condition and the correct transmitted address. The R/
W
Bit determines the direction of the data.
A Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7302A/ADV7303A acts as a standard slave device on
the bus. The data on the SDA Pin is eight bits long, supporting
the 7-bit addresses plus the R/
W
Bit. It interprets the first byte
as the device address and the second byte as the starting
subaddress. The subaddress’s autoincrement allows data to be
written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without having to update all the registers.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, it will cause an imme-
diate jump to the idle condition. During a given SCLK high period,
the user should issue only one start condition, one stop condi-
tion, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7302A/ADV7303A will not issue an acknowledge and will
return to the idle condition. If in Autoincrement Mode the user
exceeds the highest subaddress, the following action will be taken:
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDA line is not pulled low on the ninth
pulse.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7302A/ADV7303A, and the part will
return to the idle condition.
Before writing to the subcarrier frequency registers, it is a require-
ment that the ADV7302A/ADV7303A has been reset at least
once since power-up.
The four Subcarrier Frequency Registers must be updated
starting with Subcarrier Frequency Register 0. The subcarrier
frequency will not update until the last subcarrier frequency
register byte has been received by the ADV7302A/ADV7303A.
Figure 17 illustrates an example of data transfer for a read sequence
and the start and stop conditions.
Figure 18 shows bus write and read sequences.
SDATA
SCLOCK
START ADRR R/
W
ACK
SUBADDRESS ACK
DATA
ACK
STOP
1–7
8
9
S
1–7
8
9
1–7
8
9
P
Figure 17. Bus Data Transfer
相關(guān)PDF資料
PDF描述
ADV7302AKST Sand Paper; Abrasive Grade:A VFN; Color:Maroon; Pack Quantity:6; Roll Length:30ft; Width:2"
ADV7303A Sand Paper; Abrasive Grade:A VFN; Color:Maroon; Pack Quantity:4; Roll Length:30ft; Width:3"
ADV7303AKST Sand Paper; Abrasive Grade:T; Color:White; Pack Quantity:3; Roll Length:30ft; Width:4"
ADV7310 Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7310KST Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7302AKST 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SD, Progressive Scan/HDTV Video Encoder with Six 11-Bit DACs
ADV7303A 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SD, Progressive Scan/HDTV Video Encoder with Six 11-Bit DACs
ADV7303AKST 制造商:Rochester Electronics LLC 功能描述:150MHZ HD 108MHZ PROG SCAN 11BIT ENC I.C - Bulk 制造商:Analog Devices 功能描述:
ADV73045701 制造商:LG Corporation 功能描述:Frame Assembly
ADV73045702 制造商:LG Corporation 功能描述:Frame Assembly
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