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參數(shù)資料
| 型號： | ADV7192KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP80 |
| 封裝： | LQFP-80 |
| 文件頁數(shù)： | 36/69頁 |
| 文件大?。?/td> | 664K |
| 代理商： | ADV7192KST |
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ADV7192
–36–
REV. 0
Chroma Delay Control (MR94–MR95)
The Chroma signal can be delayed by up to 8 clock cycles at
27 MHz using MR94–95. For further information see also
Chroma/Luma Delay Section.
TIMING REGISTER 0 (TR07–TR00)
(Address (SR4–SR0) = 0AH)
Figure 67 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7192 is in master or slave mode.
Timing Mode Selection (TR01–TR02)
These bits control the timing mode of the ADV7192. These
modes are described in more detail in the Video Timing Descrip-
tion section of the data sheet.
BLANK
Input Control (TR03)
This bit controls whether the
BLANK
input is used to accept
blank signals or whether blank signals are internally generated.
Note: When this input pin is tied high (to 5 V), the input is dis-
abled regardless of the register setting. It, therefore, should be
tied low (to Ground) to allow control over the I
2
C register.
Luma Delay (TR04–TR05)
The luma signal can be delayed by up to 222 ns (or six clock
cycles at 27 MHz) using TR04–TR05. For further information
see Chroma/Luma Delay section.
Min Luminance Value (TR06)
This bit is used to control the minimum luma output value
by the ADV7192 in 2
×
Oversampling mode and 4
×
Oversampling
mode. When this bit is set to a Logic 1, the luma is limited to
7IRE below the blank level. When this bit is set to (0), the luma
value can be as low as the sync bottom level.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
TIMING REGISTER 1 (TR17–TR10)
(Address (SR4–SR0) = 0BH)
Timing Register 1 is a 8-bit-wide register.
Figure 68 shows the various operations under the control of
Timing Register 1. This register can be read from as well written
to. This register can be used to adjust the width and position of
the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC
Width (TR10–TR11)
These bits adjust the
HSYNC
pulsewidth.
T
PCLK
= one clock cycle at 27 MHz.
HSYNC
to
VSYNC
Delay (TR13–TR12)
These bits adjust the position of the
HSYNC
output relative to
the VSYNC output.
T
PCLK
= one clock cycle at 27 MHz.
HSYNC
to
VSYNC
Rising Edge Delay (TR14–TR15)
When the ADV7192 is in Timing Mode 1, these bits adjust the
position of the HSYNC output relative to the VSYNC output
rising edge.
T
PCLK
= one clock cycle at 27 MHz.
VSYNC
Width (TR14–TR15)
When the ADV7192 is configured in Timing Mode 2, these bits
adjust the
VSYNC
pulsewidth.
T
PCLK
= one clock cycle at 27 MHz.
HSYNC
to Pixel Data Adjust (TR16–TR17)
This enables the
HSYNC
to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be swapped.
MR97
MR96
MR95
MR94
MR93
MR92
MR91
MR90
ZERO MUST
BE WRITTEN
TO THESE BITS
MR97 MR96
CHROMA
DELAY CONTROL
MR95 MR94
0 0 0ns DELAY
0
1
1
0
1
1
148ns DELAY
296ns DELAY
RESERVED
UNDERSHOOT
LIMITER
MR91 MR90
0 0 DISABLED
0
1
1
0
1
1
–11 IRE
–6 IRE
–1.5 IRE
0
1
DISABLE
ENABLE
MR93
BLACK BURST
LUMA DAC
BLACK BURST
Y DAC
MR92
0
1
DISABLE
ENABLE
Figure 66. Mode Register 9 (MR9)
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
0
LUMA MIN =
SYNC BOTTOM
LUMA MIN =
BLANK –7.5 IRE
1
TR06
MIN LUMINANCE VALUE
0
1
ENABLE
DISABLE
TR03
BLANK
INPUT
CONTROL
TIMING
REGISTER RESET
TR07
0
1
SLAVE TIMING
MASTER TIMING
TR00
MASTER/SLAVE
CONTROL
LUMA DELAY
TR05 TR04
0 0 0ns DELAY
0
1
1
0
1
1
74ns DELAY
148ns DELAY
222ns DELAY
TR02 TR01
0 0 MODE 0
0
1
1
0
1
1
MODE 1
MODE 2
MODE 3
TIMING MODE
SELECTION
Figure 67. Timing Register 0
相關(guān)PDF資料 |
PDF描述 |
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| ADV7192 | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7194KST | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| ADV7194 | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7194 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| ADV7194KST | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:PROFESSIONAL/HDTV NTSC/PAL ENCODER I.C. - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7194KSTZ | 功能描述:IC ENCODER VIDEO EXT-10 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
| ADV7195 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
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