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參數(shù)資料
| 型號： | ADV7192KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP80 |
| 封裝： | LQFP-80 |
| 文件頁數(shù)： | 28/69頁 |
| 文件大小： | 664K |
| 代理商： | ADV7192KST |
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ADV7192
–28–
REV. 0
MPU PORT DESCRIPTION
The ADV7192 support a two-wire serial (I
2
C-compatible)
microprocessor bus driving multiple peripherals. Two inputs,
Serial Data (SDA) and Serial Clock (SCL), carry information
between any device connected to the bus. Each slave device is
recognized by a unique address. The ADV7192 has four possible
slave addresses for both read and write operations. These are
unique addresses for each device and are illustrated in Figure 52
and Figure 54. The LSB sets either a read or write operation.
Logic Level 1 corresponds to a read operation while Logic Level
0 corresponds to a write operation. A1 is set by setting the ALSB
pin of the ADV7192 to Logic Level 0 or Logic Level 1. When
ALSB is set to 0, there is greater input bandwidth on the I
2
C
lines, which allows high speed data transfers on this bus. When
ALSB is set to 1, there is reduced input bandwidth on the I
2
C
lines, which means that pulses of less than 50 ns will not pass
into the I
2
C internal controller. This mode is recommended for
noisy systems.
1
X
1
0
1
0
1
A1
ADDRESS
CONTROL
SETUP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 52. Slave Address
To control the various devices on the bus the following protocol
must be followed. First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start con-
dition and shift the next eight bits (7-bit address + R/
W
bit). The
bits are transferred from MSB down to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an acknowl-
edge bit. All other devices withdraw from the bus at this point
and maintain an idle condition. The idle condition is where
the device monitors the SDA and SCL lines waiting for the
start condition and the correct transmitted address. The R/
W
bit
determines the direction of the data.
A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.
DATA
A(S)
S
SLAVE ADDR
A(S)
SUB ADDR
A(S)
LSB = 0
LSB = 1
DATA
A
(S) P
S
SLAVE ADDR
A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
A
(M)
DATA
P
WRITE
SEQUENCE
READ
SEQUENCE
A
(S) = NO ACKNOWLEDGE BY SLAVE
A
(M) = NO ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
Figure 54. Write and Read Sequences
The ADV7192 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long supporting the 7-bit
addresses plus the R/
W
bit. It interprets the first byte as the device
address and the second byte as the starting subaddress. The
subaddresses autoincrement allowing data to be written to or read
from the starting subaddress. A data transfer is always terminated
by a stop condition. The user can also access any unique subaddress
register on a one-by-one basis without having to update all the
registers. There is one exception. The Subcarrier Frequency
Registers should be updated in sequence, starting with Subcarrier
Frequency Register 0. The autoincrement function should be
then used to increment and access Subcarrier Frequency Registers
1, 2, and 3. The Subcarrier Frequency Registers should not be
accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then, these cause an
immediate jump to the idle condition. During a given SCL high
period the user should issue only one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7192 will not issue an acknowledge and will return to the
idle condition. If, in autoincrement mode, the user exceeds the
highest subaddress, then the following action will be taken:
1. In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues
a no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is where the SDA line is not pulled
low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7192 and the part will return to the
idle condition.
8
9
1 7
8
9
1 7
8
9
P
S
START ADDR R/
W
ACK SUBADDRESS ACK
DATA
ACK
STOP
SDATA
SCLOCK
1 7
Figure 53. Bus Data Transfer
Figure 53 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 54 shows bus write and read sequences.
相關PDF資料 |
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|---|---|
| ADV7192 | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7194KST | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| ADV7194 | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7194 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| ADV7194KST | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:PROFESSIONAL/HDTV NTSC/PAL ENCODER I.C. - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7194KSTZ | 功能描述:IC ENCODER VIDEO EXT-10 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
| ADV7195 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
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