參數(shù)資料
型號： ADV7192KST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
中文描述： COLOR SIGNAL ENCODER, PQFP80
封裝： LQFP-80
文件頁數(shù)： 20/69頁
文件大?。?/td> 664K
代理商： ADV7192KST
ADV7192
–
20
–
REV. 0
YUV LEVELS
This functionality allows the ADV7192 to output SMPTE levels
or Betacam levels on the Y output when configured in PAL or
NTSC mode.
Sync
Betacam
286 mV
SMPTE
300 mV
MII
300 mV
As the data path is branched at the output of the filters, the luma
signal relating to the CVBS or S-Video Y/C output is unaltered.
Only the Y output of the YCrCb outputs is scaled. This control
allows color component levels to have a peak-peak amplitude of
700 mV, 1000 mV or the default values of 934 mV in NTSC and
700 mV in PAL. (Mode Register 5.)
Video
714 mV
700 mV
700 mV
16-BIT INTERFACE
It is possible to input data in 16-bit format. In this case, the
interface only operates if the data is accompanied by separate
HSYNC
/
VSYNC
/
BLANK
signals. Sixteen-bit mode is not
available in Slave Mode 0 since EAV/SAV timing codes are
used. (Mode Register 8.)
4 OVERSAMPLING AND INTERNAL PLL
It is possible to operate all six DACs at 27 MHz (2
×
Oversam-
pling) or 54 MHz (4
×
Oversampling).
The ADV7192 is supplied with a 27 MHz clock synced with the
incoming data. Two options are available: to run the device
throughout at 27 MHz or to enable the PLL. In the latter case,
even if the incoming data runs at 27 MHz, 4
×
Oversampling and
the internal PLL will output the data at 54 MHz.
NOTE
In 4
×
Oversampling Mode the requirements for the optional
output filters are different from those in 2
×
Oversampling. (Mode
Register 1, Mode Register 6.) See Appendix 6.
ENCODER
CORE
2
I
N
T
E
R
P
O
L
A
T
I
O
N
6
D
A
C
O
U
T
P
U
T
S
54MHz
OUTPUT
ENCODE
ADV7192
PLL
54MHz
MPEG2
PIXEL BUS
27MHz
Figure 35. PLL and 4
×
Oversampling Block Diagram
–
30dB
0dB
6.75MHz
13.5MHz
27.0MHz
40.5MHz
54.0MHz
2 FILTER
REQUIREMENTS
4 FILTER
REQUIREMENTS
Figure 36. Output Filter Requirements in 2
×
and 4
×
Over-
sampling Mode
VIDEO TIMING DESCRIPTION
The ADV7192 is intended to interface to off-the-shelf MPEG1
and MPEG2 Decoders. As a consequence, the ADV7192 accepts
4:2:2 YCrCb Pixel Data via a CCIR-656 Pixel Port and has
several Video Timing Modes of operation that allow it to be
configured as either System Master Video Timing Generator or
a Slave to the System Video Timing Generator. The ADV7192
generates all of the required horizontal and vertical timing periods
and levels for the analog video outputs.
The ADV7192 calculates the width and placement of analog
sync pulses, blanking levels, and color burst envelopes. Color
bursts are disabled on appropriate lines and serration and equal-
ization pulses are inserted where required.
In addition the ADV7192 supports a PAL or NTSC square pixel
operation. The part requires an input pixel clock of 24.5454 MHz
for NTSC square pixel operation and an input pixel clock of
29.5 MHz for PAL square pixel operation. The internal horizontal
line counters place the various video waveform sections in the cor-
rect location for the new clock frequencies.
The ADV7192 has four distinct Master and four distinct Slave
timing configurations. Timing Control is established with
the bidirectional
HSYNC
,
BLANK
and
VSYNC
pins. Tim-
ing Register 1 can also be used to vary the timing pulsewidths
and where they occur in relation to each other. (Mode Regis-
ter 2, Timing Register 0, 1.)
RESET
SEQUENCE
When
RESET
becomes active the ADV7192 reverts to the default
output configuration (see Appendix 8 for register settings). The
ADV7192 internal timing is under the control of the logic level
on the NTSC_PAL pin.
When
RESET
is released Y, Cr, Cb values corresponding to a
black screen are input to the ADV7192. Output timing signals
are still suppressed at this stage. DACs A, B, C are switched off
and DACs D, E, F are switched on.
When the user requires valid data, Pixel Data Valid Control is
enabled (MR26 = 1) to allow the valid pixel data to pass through
the encoder. Digital output timing signals become active and the
encoder timing is now under the control of the Timing Regis-
ters. If at this stage, the user wishes to select a different video
standard to that on the NTSC_PAL pin, Standard I
2
C Control
should be enabled (MR25 = 1) and the video standard required
is selected by programming Mode Register 0 (Output Video Stan-
dard Selection). Figure 37 illustrates the
RESET
sequence timing.
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