參數(shù)資料
型號： ADV7190KST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
中文描述： COLOR SIGNAL ENCODER, PQFP64
封裝： LQFP-64
文件頁數(shù)： 35/69頁
文件大小： 628K
代理商： ADV7190KST
ADV7190/ADV7191
–35–
REV. 0
TIMING REGISTER 0 (TR07–TR00)
(Address (SR4–SR0) = 0AH)
Figure 60 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7190/ADV7191 is in master or
slave mode.
Timing Mode Selection (TR01–TR02)
These bits control the timing mode of the ADV7190/ADV7191.
These modes are described in more detail in the Video Tim-
ing Description and
RESET
Sequence sections of the data sheet.
BLANK
Input Control (TR03)
This bit controls whether the
BLANK
input is used to accept
blank signals or whether blank signals are internally generated.
Note: When this input pin is tied high (to 5 V), the input is dis-
abled regardless of the register setting. It, therefore, should be
tied low (to Ground) to allow control over the I
2
C register.
Luma Delay (TR04–TR05)
The luma signal can be delayed by up to 222 ns (or six clock
cycles at 27 MHz) using TR04–TR05. For further information
see Chroma/Luma Delay section.
Min Luminance Value (TR06)
This bit is used to control the minimum luma output value
by the ADV7190/ADV7191 in 2
×
Oversampling Mode (MR 16 =
0). When this bit is set to a Logic 1, the luma is limited to 7.5IRE
below the blank level. When this bit is set to (0), the luma value
can be as low as the sync bottom level (40IRE below blanking).
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset, or changing to a new timing mode.
TIMING REGISTER 1
(TR17–TR10)
(Address (SR4–SR0) = 0BH)
Timing Register 1 is an 8-bit-wide register.
Figure 61 shows the various operations under the control of
Timing Register 1. This register can be read from as well written
to. This register can be used to adjust the width and position of
the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC
Width (TR10–TR11)
These bits adjust the
HSYNC
pulsewidth.
T
PCLK
= one clock cycle at 27 MHz.
HSYNC
to
VSYNC
Delay Control (TR12–TR13)
These bits adjust the position of the
HSYNC
output relative to
the
VSYNC
output.
T
PCLK
= one clock cycle at 27 MHz.
HSYNC
to
VSYNC
Rising Edge Control (TR14–TR15)
When the ADV7190/ADV7191 is in Timing Mode 1, these bits
adjust the position of the
HSYNC
output relative to the
VSYNC
output rising edge.
T
PCLK
= one clock cycle at 27 MHz.
VSYNC
Width (TR14–TR15)
When the ADV7190/ADV7191 is configured in Timing Mode
2, these bits adjust the
VSYNC
pulsewidth.
T
PCLK
= one clock cycle at 27 MHz.
HSYNC
to Pixel Data Adjust (TR16–TR17)
This enables the
HSYNC
to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be swapped.
This adjustment is available in both master and slave timing
modes.
T
PCLK
= one clock cycle at 27 MHz.
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
0
LUMA MIN =
SYNC BOTTOM
LUMA MIN =
BLANK
–
7.5 IRE
1
TR06
MIN LUMINANCE VALUE
0
1
ENABLE
DISABLE
TR03
BLANK
INPUT
CONTROL
TIMING
REGISTER RESET
TR07
0
1
SLAVE TIMING
MASTER TIMING
TR00
MASTER/SLAVE
CONTROL
LUMA DELAY
TR05 TR04
0 0 0ns DELAY
0
1
1
0
1
1
74ns DELAY
148ns DELAY
222ns DELAY
TR02 TR01
0 0 MODE 0
0
1
1
0
1
1
MODE 1
MODE 2
MODE 3
TIMING MODE
CONTROL
Figure 60. Timing Register 0
相關(guān)PDF資料
PDF描述
ADV7191 Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
ADV7191KST Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
ADV7190 Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
ADV7192KST Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
ADV7192 Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7190KSTZ 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP
ADV7191 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
ADV7191KST 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:54M 4X STD DEF ENCODER NON-MACRO I.C. - Tape and Reel
ADV7191KSTZ 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER
ADV7192 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
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