Bit1 Address Register Bit Description 7 6 5 43210Comments Notes 0x0A Br" />
參數(shù)資料
型號(hào)： ADV7184BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 98/112頁(yè)
文件大?。?/td> 0K
描述： IC DECODER VID SDTV MULTI 80LQFP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 視頻解碼器
應(yīng)用： 投影儀，錄音機(jī)，安全
電壓 - 電源，模擬： 3.15 V ~ 3.45 V
電壓 - 電源，數(shù)字： 1.65 V ~ 2 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤(pán)
ADV7184
Rev. A | Page 86 of 112
Bit1
Address
Register
Bit Description
7 6 5 43210Comments
Notes
0x0A
Brightness Register
BRI [7:0]. These bits control the brightness of
the video signal.
0 0 0 0 0 0 0 0
0x00 = 0 mV.
0x7F = +204 mV.
0x80 = 204 mV.
0x0B
Hue Register
HUE [7:0]. These bits contain the value for the
color hue adjustment.
0 0 0 0 0 0 0 0
Hue range = 90° to +90°.
0 Free-run mode dependent on
DEF_VAL_AUTO_EN
DEF_VAL_EN. Default value enable.
1 Force free-run mode on and
output blue screen
0
Disable free-run mode
DEF_VAL_AUTO_EN. Default value.
1
Enable automatic free-run mode
(blue screen)
When lock is lost, free-run mode can
be enabled to output stable timing,
clock, and a set color.
0x0C
Default Value Y
DEF_Y [5:0]. Default value Y. These bits hold
the Y default value.
0 0 1 1 0 1
Y [7:0] = {DEF_Y [5:0], 0, 0}
Default Y value output in free-run
mode.
0x0D
Default Value C
DEF_C [7:0]. Default value C. The Cr and Cb
default values are defined in these bits.
0 1 1 1 1 1 0 0 Cr [7:0] = {DEF_C [7:4], 0, 0, 0, 0}
Cb [7:0] = {DEF_C [3:0], 0, 0, 0, 0}
Default Cb/Cr value output in free-run
mode. Default values give blue screen
output.
Reserved.
0 0 0 0 0 Set as default
0
Access user map
SUB_USR_EN. This bit enables the user to
access the user sub map.
1
Access user sub map
See
0x0E
Analog Devices
Control
Reserved.
0 0
Set as default
Reserved.
0 Set to default
0
FB input operational
FB_PWRDN.
1
FB input in power-saving mode
0
Chip power-down controlled by pin
PDBP. Power-down bit priority. This bit selects
between the PWRDN bit and the PWRDN pin.
1
Bit has priority (pin disregarded)
This bit must be set to 1 for the PWRDN
bit to power down the part.
Reserved.
0 0
Set to default
0
System functional
PWRDN. Power-down. This bit places the
decoder in full power-down mode.
1
Powered down
The PDBP bit must be set to 1 for the
PWRDN bit to power down the part
(see PDBP, 0x0F Bit 2).
Reserved.
0
Set to default
0
Normal operation
0x0F
Power Management
RES. Chip Reset. This bit loads all I2C bits with
default values.
1
Start reset sequence
Executing reset takes approximately
2 ms. This bit is self-clearing.
IN_LOCK.
x
1 = in lock (now)
LOST_LOCK.
x
1 = lost lock (since last read)
FSC_LOCK.
x
1 = FSC lock (now)
FOLLOW_PW.
x
1 = peak white AGC mode active
Provides information about the
internal status of the decoder.
0 0 0
NTSM M/J
0 0 1
NTSC 443
0 1 0
PAL M
0 1 1
PAL 60
1 0 0
PAL B/G/H/I/D
1 0 1
SECAM
1 1 0
PAL Combination N
AD_RESULT [2:0]. Autodetection result. These
bits report the standard of the input video.
1 1 1
SECAM 525
Detected standard.
0x10
Status Register 1
(Read Only)
COL_KILL.
x
1 = color kill is active
Color kill.
0x11
IDENT (Read Only)
IDENT [7:0]. These bits provide identification
on the revision of the part.
x x x x
x
MVCS DET.
x
MV color striping detected
1 = detected.
MVCS T3.
x
MV color striping type
0 = Type 2; 1 = Type 3.
MV_PS DET.
x
MV pseudosync detected
1 = detected.
MV_AGC DET.
x
MV AGC pulses detected
1 = detected.
LL_NSTD.
x
Nonstandard line length
1 = detected.
FSC_NSTD.
x
FSC frequency nonstandard
1 = detected.
0x12
Status Register 2
(Read Only)
Reserved.
x x
0x13
INST_HLOCK.
x
1 = horizontal lock achieved
Unfiltered.
Status Register 3
(Read only)
GEMD.
x
1 = Gemstar data detected
When the GEMD bit goes high, it
remains high until the end of the
active video lines in that field.
SD_OP_50Hz.
x
SD field rate detect
0 = SD 60 Hz detected;
1 = SD 50 Hz detected.
CVBS.
x
Result of composite/S-video
autodetection
0 = Y/C; 1 = CVBS.
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