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參數(shù)資料
| 型號(hào)： | ADV7184BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DECODER VID SDTV MULTI 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 投影儀，錄音機(jī)，安全 |
| 電壓 - 電源，模擬： | 3.15 V ~ 3.45 V |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 2 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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ADV7184
Rev. A | Page 11 of 112
Mnemonic
Type
Description
Pin No.
67
SDA
I/O
I2C Port Serial Data Input/Output.
68
SCLK
I
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
66
ALSB
I
This pin selects the I2C address for the ADV7184. ALSB set to Logic 0 sets the address for
a write to 0x40; set to Logic 1 sets the address to 0x42.
64
RESET
I
System Reset Input (active low). A minimum low reset pulse width of 5 ms is required to reset the
ADV7184 circuitry.
27
LLC1
O
Line-Locked Clock 1. This is a line-locked output clock for the pixel data output by the ADV7184.
Nominally 27 MHz, but varies according to video line length.
26
LLC2
O
Line-Locked Clock 2. This is a divide-by-2 version of the LLC1 output clock for the pixel data
output by the ADV7184. Nominally 13.5 MHz, but varies according to video line length.
29
XTAL
I
Crystal Input. This is the input pin for the 28.63636 MHz crystal, or it can be overdriven by an
external 3.3 V, 28.63636 MHz clock oscillator source. In crystal mode, the crystal must be a
fundamental crystal.
28
XTAL1
O
This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external
3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7184. In crystal mode, the
crystal must be a fundamental crystal.
36
PWRDN
I
Logic 0 on this pin places the ADV7184 in a power-down mode. Refer to the I2C Register Maps
section for more options on power-down modes for the ADV7184.
79
OE
I
When set to Logic 0, OE enables the pixel output bus, P15 to P0 of the ADV7184. Logic 1 on the
OE pin places P15 to P0, HS, VS, and SFL into a high impedance state.
37
ELPF
I
The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 52.
12
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices, Inc., digital video
encoder.
63
SOY
I
SYNC on Y. This input pin should only be used with the standard detection and identification function
(see the Standard Detection and Identification section). This pin should be connected to the Y
signal of a component input for standard identification function.
51
REFOUT
O
Internal Voltage Reference Output. Refer to Figure 52 for a recommended capacitor network for
this pin.
52
CML
O
Common-Mode Level. The CML pin is a common-mode level for the internal ADCs. Refer to
Figure 52 for a recommended capacitor network for this pin.
48, 49
CAPY1,
CAPY2
I
ADC Capacitor Network. Refer to Figure 52 for a recommended capacitor network for this pin.
54, 55
CAPC1,
CAPC2
I
ADC Capacitor Network. Refer to Figure 52 for a recommended capacitor network for this pin.
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