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參數(shù)資料
| 型號(hào)： | ADV7183KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| 中文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 33/41頁 |
| 文件大?。?/td> | 484K |
| 代理商： | ADV7183KST |
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REV. 0
ADV7183
–33–
Table XLIV. Miscellaneous Gain Control Register (Subaddress 33)
Bit Description
PW_UPD
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
1
0
1
Update Gain Once per Line
Update Gain Once per Field
Lines 33 to 310
Lines 33 to 270
PAL-133 NTSC-122
PAL-125 NTSC-115
PAL-120 NTSC-110
PAL-115 NTSC-105
PAL-110 NTSC-100
PAL-105 NTSC-100
PAL-100 NTSC-100
PAL-100 NTSC-100
Set to One
Color Kill Disabled
Color Kill Enabled
Set to One
AV_AL
2
0
1
MIRE[2:0]
3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RESERVED
CKE
1
0
1
RESERVED
NOTES
1
Peak White Update. Determines the gain based on measurements taken from the active video; this bit determines the rate of gain change. LAGC[1:0] must be set to
the appropriate mode to enable peak white or average video in the first case.
2
Average Brightness Active Lines. Allows the selection between two ranges of active video to determine the average brightness.
3
Max IRE. Sets the max I/p IRE level depending on the video standard.
4
Color Kill Enable. Allows the optional color kill function to be switched on or off.
1
4
Table XLV. HSync Position Control 1 Register (Subaddress 34)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
RESERVED
HSE[9:8]
1
0
0
1
1
1
1
Set to One
HSync ends after HSE[9:0] pixel after falling edge
of HSync.
HSync starts after HSB[9:0] pixel after the falling
edge of HSync.
HSB[9:8]
2
0
0
NOTES
1
HSync End. Allows the positioning of the HSync output within the video line.
2
HSync Begin. Allows the positioning of HSync output within the video line.
Table XLVI. HSync Position Control 2 Register (Subaddress 35)
Bit Description
HSB[7:0]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
0
0
0
0
0
0
1
1
1
Using HSB[9:0] and HSE[9:0] the user can program the position and length of HSync output signal.
Table XLVII. HSync Position Control 3 Register (Subaddress 36)
Bit Description
HSE[7:0]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
0
0
0
0
0
0
1
1
1
Using HSB[9:0] and HSE[9:0] the user can program the position and length of HSync output signal.
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