參數(shù)資料
型號(hào)： ADV7171KSUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/64頁(yè)
文件大小： 0K
描述： IC DAC VIDEO ENC NTSC 44TQFP
產(chǎn)品培訓(xùn)模塊： Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，視頻播放器
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 44-TQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 786 (CN2011-ZH PDF)
ADV7170/ADV7171
Rev. C | Page 36 of 64
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3 TO 0 (PCE15 TO PCE0, PCO15
TO PCO0)/(TXE15 TO TXE0, TXO15 TO TXO0)
(Subaddress [SR4–SR0] = 12H to 15H)
These 8-bit-wide registers are used to enable the NTSC
pedestal/PAL teletext on a line-by-line basis in the vertical
blanking interval for both odd and even fields. Figure 48 and
Figure 49 show the four control registers. A Logic Level 1 in any
of the bits of these registers has the effect of turning the pedestal
off on the equivalent line when used in NTSC. A Logic Level 1
in any of the bits of these registers has the effect of turning on
teletext on the equivalent line when used in PAL.
FIELD 1/3
PCO6
PCO5
PCO3
PCO1
PCO4
PCO2
PCO0
PCO7
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO14
PCO13
PCO11
PCO9
PCO12
PCO10
PCO8
PCO15
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3
FIELD 2/4
PCE6
PCE5
PCE3
PCE1
PCE4
PCE2
PCE0
PCE7
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE14
PCE13
PCE11
PCE9
PCE12
PCE10
PCE8
PCE15
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4
00221-048
Figure 48. Pedestal Control Registers
FIELD 1/3
FIELD 2/4
TXO6
TXO5
TXO3
TXO1
TXO4
TXO2
TXO0
TXO7
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 8 LINE 7
TXO14
TXO13
TXO11
TXO9
TXO12
TXO10
TXO8
TXO15
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXE6
TXE5
TXE3
TXE1
TXE4
TXE2
TXE0
TXE7
TXE14
TXE13
TXE11
TXE9
TXE12
TXE10
TXE8
TXE15
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 8
LINE 7
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
00221-049
Figure 49. Teletext Control Registers
TELETEXT REQUEST CONTROL REGISTER TC07
(TC07 TO TC00)
(Address [SR4 to SR0] = 19H)
Teletext control register is an 8-bit-wide register. See Figure 50.
TTXREQ Rising Edge Control (TC07 to TC04)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a maximum
of 15 CLOCK cycles. See Figure 59.
TTXREQ Falling Edge Control (TC03 to TC00)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of
15 CLOCK cycles. This controls the active window for teletext
data. Increasing this value reduces the amount of teletext bits
below the default of 360. If Bit TC03 to Bit TC00 are 00Hex
when bits TC07 to TC04 are changed, the falling edge of
TTXREQ tracks that of the rising edge (that is, the time
between the falling and rising edge remains constant).
CGMS_WSS REGISTER 0 C/W0 (C/W07 TO C/W00)
(Address [SR4 to SR0] = 16H)
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51
shows the operations under the control of this register.
C/W0 BIT DESCRIPTION
CGMS Data Bits (C/W03 to C/W00)
These four data bits are the final four bits of the CGMS data
output stream. Note it is CGMS data ONLY in these bit
positions; that is, WSS data does not share this location.
CGMS CRC Check Control (C/W04)
When this bit is enabled (1), the last six bits of the CGMS data
(that is, the CRC check sequence) are calculated internally by
the ADV7170/ADV7171. If this bit is disabled (0), the CRC
values in the register are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
When this bit is set (1), CGMS is enabled for odd fields. Note
this is valid only in NTSC mode.
CGMS Even Field Control (C/W06)
When this bit is set (1), CGMS is enabled for even fields. Note
this is valid only in NTSC mode.
WSS Control (C/W07)
When this bit is set (1), wide screen signaling is enabled. Note
this is valid only in PAL mode.
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