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參數(shù)資料
| 型號： | ADV7171KSUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO ENC NTSC 44TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Interfacing AV Converters to Blackfin Processors |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | 機頂盒，視頻播放器 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 786 (CN2011-ZH PDF) |
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ADV7170/ADV7171
Rev. C | Page 34 of 64
TR01
TR00
TR07
TR02
TR03
TR05
TR06
TR04
TIMING
REGISTER RESET
TR07
BLANK INPUT
CONTROL
0
ENABLE
1
DISABLE
TR03
PIXEL PORT
CONTROL
0
8 BIT
1
16 BIT
TR06
MASTER/SLAVE
CONTROL
0
SLAVE TIMING
1
MASTER TIMING
TR00
LUMA DELAY
0
0ns DELAY
0
1
74ns DELAY
1
0
148ns DELAY
1
222ns DELAY
TR05 TR04
TIMING MODE
SELECTION
0
MODE 0
0
1
MODE 1
1
0
MODE 2
1
MODE 3
TR02 TR01
00221-043
Figure 43. Timing Register 0
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7170/ADV7171 is in
Master or Slave Mode.
Timing Mode Selection (TR02 to TR01)
These bits control the timing mode of the ADV7170/ ADV7171.
These modes are described in more detail in
the Timing and Control section.
BLANK Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode.
Luma Delay (TR05 to TR04)
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Control (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected, the data will be set up on
Pin P7 to Pin P0.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the
internal timing counters. This bit should be toggled after
power-up, reset or changing to a new timing mode.
TIMING MODE REGISTER 1 (TR17 TO TR10)
(Address (SR4 to SR0) = 08H)
Timing Register 1 is an 8-bit-wide register.
Figure 44 shows the various operations under the control of
Timing Register 1. This register can be read from as well written
to. This register can be used to adjust the width and position of
the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR11 to TR10)
These bits adjust the HSYNC pulse width.
HSYNC to FIELD/VSYNC Delay (TR13 to TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD Rising Edge Delay (TR15 to TR14)
When the ADV7170/ADV7171 are in Timing Mode 1, these
bits adjust the position of the HSYNC output relative to the
FIELD output rising edge.
VSYNC Width (TR15 to TR14)
When the ADV7170/ADV7171 are configured in Timing
Mode 2, these bits adjust the VSYNC pulse width.
HSYNC to Pixel Data Adjust (TR17 to TR16)
This enables the HSYNC to be adjusted with respect to the pixel
data. This allows the Cr and Cb components to be swapped.
This adjustment is available in both master timing mode and
slave timing mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7171KSUZ-REEL | 功能描述:IC DAC VIDEO ENC NTSC 44TQFP TR RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7171KSZ | 功能描述:IC DAC VIDEO ENC NTSC 44-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7171KSZ | 制造商:Analog Devices 功能描述:IC, VIDEO ENCODER, 10BIT, MQFP-44 |
| ADV7171KSZ-REEL | 功能描述:IC DAC VIDEO ENC NTSC 44-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7171SU | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management |
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