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參數資料
| 型號： | ADV601 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 視頻Codec |
| 英文描述： | Low Cost Multiformat Video Codec |
| 中文描述： | 低成本多格式視頻解碼器 |
| 文件頁數： | 19/52頁 |
| 文件大?。?/td> | 606K |
| 代理商： | ADV601 |
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ADV601
–19–
REV. 0
Host Interface Pins
(
Continued
)
Name
Pins
I/O
Description
BE0
–
BE3
(Cont.)
4
I
Some important notes for 8- and 16-bit interfaces are as follows:
When using these byte enable pins, the byte order is always the lowest byte
to the higher bytes.
The ADV601 advances to the next 32-bit compressed data FIFO location
after the
BE3
pin is asserted then de-asserted (when accessing the Com-
pressed Data register); so the FIFO location only advances when and if the
host reads or writes the MSB of a FIFO location.
The ADV601 advances to the next 16-bit indirect register after the
BE1
pin
is asserted then de-asserted; so the register selection only advances when
and if the host reads or writes the MSB of a 16-bit indirect register.
Host Chip Select. This pin operates as follows:
LO Qualifies Host Interface control signals
HI Three-states DATA[31:0] pins
Host Write. Host register writes occur on the rising edge of this signal.
Host Read. Host register reads occur on the low true level of this signal.
Host Acknowledge. The ADV601 acknowledges completion of a Host Inter-
face access by asserting this pin. Most Host Interface accesses (other than the
compressed data register access) result in
ACK
being held high for at least one
wait cycle, but some exceptions to that rule are as follows:
A full FIFO during decode operations causes the ADV601 to de-assert
(drive HI) the
ACK
pin, holding off further writes of compressed data until
the FIFO has one available location.
An empty FIFO during encode operations causes the ADV601 to de-assert
(drive HI) the
ACK
pin, holding off further reads until one location is filled.
FIFO Error. This condition indicates that the host has been unable to keep up
with the ADV601’s compressed data supply or demand requirements. If this
condition occurs for a long time during encode, the data stream may be cor-
rupted. If this condition occurs for a long time during decode, the video out-
put may be corrupted. The state of this pin also appears in the Interrupt Mask/
Status register. Use the interrupt mask to assert a Host interrupt (
HIRQ
pin)
based on the state of the FIFO_ERR pin. This pin operates as follows:
LO No FIFO Error condition (FIFOERR bit LO)
HI FIFO overflow (encode) or underflow (decode) (FIFOERR bit HI)
FIFO Service Request. This pin is an active high signal indicating that the
FIFO needs to be serviced by the host. (see FIFO Control register). The state
of this pin also appears in the Interrupt Mask/Status register. Use the interrupt
mask to assert a Host interrupt (
HIRQ
pin) based on the state of the FIFO_SRQ
pin. This pin operates as follows:
LO No FIFO Service Request condition (FIFOSRQ bit LO)
HI FIFO needs service is nearly full (encode) or nearly empty (decode)
During encode, FIFO_SRQ is LO when the SWR bit is cleared (0) and goes
HI when the FIFO is nearly full (see FIFO Control register).
During decode, FIFO_SRQ is HI when the SWR bit is cleared (0), because
FIFO is empty, and goes LO when the FIFO is filled beyond the nearly empty
condition (see FIFO Control register).
CS
1
I
WR
RD
ACK
1
1
1
I
I
O
FIFO_ERR
1
O
FIFO_SRQ
1
O
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相關代理商/技術參數 |
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