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參數(shù)資料
| 型號： | ADUC824BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁數(shù)： | 7/68頁 |
| 文件大?。?/td> | 1060K |
| 代理商： | ADUC824BS |
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REV. B
–7–
ADuC824
Parameter
ADuC824BS
Test Conditions/Comments
Unit
POWER REQUIREMENTS (continued)
Power Supply Currents Normal Mode
17, 18
DV
DD
Current
4
2.1
170
15
8
170
DV
DD
= 4.75 V to 5.25 V, Core CLK = 1.57 MHz
DV
DD
= 2.7 V to 3.6 V, Core CLK = 1.57 MHz
AV
DD
= 5.25 V, Core CLK = 1.57 MHz
DV
DD
= 4.75 V to 5.25 V, Core CLK = 12.58 MHz
DV
DD
= 2.7 V to 3.6 V, Core CLK = 12.58 MHz
AV
DD
= 5.25 V, Core CLK = 12.58 MHz
mA max
mA max
μ
A max
mA max
mA max
μ
A max
AV
DD
Current
DV
DD
Current
AV
DD
Current
Power Supply Currents Idle Mode
17, 18
DV
DD
Current
1.2
750
140
2
1
140
DV
DD
= 4.75 V to 5.25 V, Core CLK = 1.57 MHz
DV
DD
= 2.7 V to 3.6 V, Core CLK = 1.57 MHz
Measured @ AV
DD
= 5.25 V, Core CLK = 1.57 MHz
μ
A typ
DV
DD
= 4.75 V to 5.25 V, Core CLK = 12.58 MHz
DV
DD
= 2.7 V to 3.6 V, Core CLK = 12.58 MHz
Measured at AV
DD
= 5.25 V, Core CLK = 12.58 MHz
μ
A typ
Core CLK = 1.57 MHz or 12.58 MHz
DV
DD
= 4.75 V to 5.25 V, Osc. On, TIC On
DV
DD
= 2.7 V to 3.6 V, Osc. On, TIC On
Measured at AV
DD
= 5.25 V, Osc. On or Osc. Off
DV
DD
= 4.75 V to 5.25 V, Osc. Off
DV
DD
= 2.7 V to 3.6 V, Osc. Off
Core CLK = 1.57 MHz, AV
DD
= DV
DD
= 5 V
mA max
μ
A typ
AV
DD
Current
DV
DD
Current
mA typ
mA typ
AV
DD
Current
Power Supply Currents Power-Down Mode
17, 18
DV
DD
Current
50
20
1
20
5
μ
A max
μ
A max
μ
A max
μ
A max
μ
A typ
AV
DD
Current
DV
DD
Current
Typical Additional Power Supply Currents
(AI
DD
and DI
DD
)
PSM Peripheral
Primary ADC
Auxiliary ADC
DAC
Dual Current Sources
50
1
500
150
400
μ
A typ
mA typ
μ
A typ
μ
A typ
μ
A typ
NOTES
Temperature Range: –40
°
C to +85
°
C.
2
These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release.
3
System Zero-Scale Calibration can remove this error.
4
The primary ADC is factory calibrated at 25
°
C with AV
= DV
= 5 V yielding this full-scale error of 10
μ
V. If user power supply or temperature conditions are
significantly different than these, an Internal Full-Scale Calibration will restore this error to 10
μ
V. A system zero-scale and full-scale calibration will remove this
error altogether.
5
Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.
6
The auxiliary ADC is factory calibrated at 25
°
C with AV
DD
= DV
DD
= 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration
will remove this error altogether.
7
DAC linearity and AC Specifications are calculated using:
reduced code range of 48 to 4095, 0 to V
REF
,
reduced code range of 48 to 3995, 0 to V
.
8
Gain Error is a measure of the span error of the DAC.
9
In general terms, the bipolar input voltage range to the primary ADC is given by Range
=
±
(V
2
RN
)/125, where:
V
= REFIN(+) to REFIN(–) voltage and V
REF
= 1.25 V when internal ADC V
is selected. RN = decimal equivalent of RN2, RN1, RN0, e.g., V
REF
= 2.5 V
and RN2, RN1, RN0 = 1, 1, 0 the Range
=
±
1.28 V. In unipolar mode the effective range is 0 V to 1.28 V in our example.
10
1.25 V is used as the reference voltage to the ADC when internal V
is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively.
11
In bipolar mode, the Auxiliary ADC can only be driven to a minimum of A
– 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar
range is still –V
to +V
; however, the negative voltage is limited to –30 mV.
12
Pins configured in I
C-compatible mode or SPI mode, pins configured as digital inputs during this test.
13
Pins configured in I
2
C-compatible mode only.
14
Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.
15
Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40
°
C, +25
°
C and +85
°
C; typical endurance at 25
°
C is 700 K cycles.
16
Retention lifetime equivalent at junction temperature (T
) = 55
°
C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6e V
will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this data sheet.
17
Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode.
Power-Down Mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in
PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR.
18
DV
DD
power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
Specifications subject to change without notice.
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