參數(shù)資料
型號(hào)： ADUC824BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/68頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x16b，4x24b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
REV. B
ADuC824
–30–
OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers
*)
These three 8-bit registers hold the 24-bit offset calibration coefficient for the Primary ADC. These registers are configured at power-
on with a factory default value of 800000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration is initiated by the user via MD2–0 bits in the ADCMODE register.
SFR Address
OF0H
Primary ADC Offset Coefficient High Byte
E3H
OF0M
Primary ADC Offset Coefficient Middle Byte
E2H
OF0L
Primary ADC Offset Coefficient Low Byte
E1H
Power-On Default Value
800000H
OF0H, OF0M, and OF0L, Respectively
Bit Addressable
No
All Three Registers
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers
*)
These two 8-bit registers hold the 16-bit offset calibration coefficient for the Auxiliary ADC. These registers are configured at power-on
with a factory default value of 8000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration is initiated by the user via the MD2–0 bits in the ADCMODE register.
SFR Address
OF1H
Auxiliary ADC Offset Coefficient High Byte
E5H
OF1L
Auxiliary ADC Offset Coefficient Low Byte
E4H
Power-On Default Value
8000H
OF1H and OF1L Respectively
Bit Addressable
No
Both Registers
GN0H/GN0M/GN0L (Primary ADC Gain Calibration Registers
*)
These three 8-bit registers hold the 24-bit gain calibration coefficient for the Primary ADC. These registers are configured at power-on
with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these
bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in the
ADCMODE register.
SFR Address
GN0H
Primary ADC Gain Coefficient High Byte
EBH
GN0M
Primary ADC Gain Coefficient Middle Byte
EAH
GN0L
Primary ADC Gain Coefficient Low Byte
E9H
Power-On Default Value
Configured at factory final test, see notes above.
Bit Addressable
No
All Three Registers
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers
*)
These two 8-bit registers hold the 16-bit gain calibration coefficient for the Auxiliary ADC. These registers are configured at power-on
with a factory calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these
bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in the
ADCMODE register.
SFR Address
GN1H
Auxiliary ADC Gain Coefficient High Byte
EDH
GN1L
Auxiliary ADC Gain Coefficient Low Byte
ECH
Power-On Default Value
Configured at factory final test, see notes above.
Bit Addressable
No
Both Registers
*These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.
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