SPECIFICATIONS1 Parameter ADuC824BS Test Conditions/Comments Unit ADC SPECIFICATIONS" />
參數(shù)資料
型號(hào): ADUC824BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 23/68頁(yè)
文件大?。?/td> 0K
描述: IC MCU 8K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 12.58MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x16b,4x24b; D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
包裝: 托盤
REV. B
–3–
ADuC824
SPECIFICATIONS1
Parameter
ADuC824BS
Test Conditions/Comments
Unit
ADC SPECIFICATIONS
Conversion Rate
5.4
On Both Channels
Hz min
105
Programmable in 0.732 ms Increments
Hz max
Primary ADC
No Missing Codes
2
24
20 Hz Update Rate
Bits min
Resolution
13
Range =
±20 mV, 20 Hz Update Rate
Bits p-p typ
18
Range =
±2.56 V, 20 Hz Update Rate
Bits p-p typ
Output Noise
See Tables IX and X Output Noise Varies with Selected
in ADC Description
Update Rate and Gain Range
Integral Nonlinearity
±15
ppm of FSR max
Offset Error
3
±3
V typ
Offset Error Drift
±10
nV/
°C typ
Full-Scale Error
4
±10
V typ
Gain Error Drift
5
±0.5
ppm/
°C typ
ADC Range Matching
±2
AIN = 18 mV
V typ
Power Supply Rejection (PSR)
113
AIN = 7.8 mV, Range =
±20 mV
dBs typ
80
AIN = 1 V, Range =
±2.56 V
dBs min
Common-Mode DC Rejection
On AIN
95
At DC, AIN = 7.8 mV, Range =
±20 mV dBs min
On AIN
113
At DC, AIN = 1 V, Range =
±2.56 V
dBs typ
On REFIN
125
At DC, AIN = 1 V, Range =
±2.56 V
dBs typ
Common-Mode 50 Hz/60Hz Rejection
2
20 Hz Update Rate
On AIN
95
50 Hz/60 Hz
±1 Hz, AIN = 7.8 mV,
dBs min
Range =
±20 mV
90
50 Hz/60 Hz
±1 Hz, AIN = 1 V,
dBs min
Range =
±2.56 V
On REFIN
90
50 Hz/60 Hz
±1 Hz, AIN = 1 V,
dBs min
Range =
±2.56 V
Normal Mode 50 Hz/60 Hz Rejection
2
On AIN
60
50 Hz/60 Hz
±1 Hz, 20 Hz Update Rate
dBs min
On REFIN
60
50 Hz/60 Hz
±1 Hz, 20 Hz Update Rate
dBs min
Auxiliary ADC
No Missing Codes
2
16
Bits min
Resolution
16
Range =
±2.5 V, 20 Hz Update Rate
Bits p-p typ
Output Noise
See Table XI
Output Noise Varies with Selected
in ADC Description
Update Rate
Integral Nonlinearity
±15
ppm of FSR max
Offset Error
3
–2
LSB typ
Offset Error Drift
1
V/°C typ
Full-Scale Error
6
–2.5
LSB typ
Gain Error Drift
5
±0.5
ppm/
°C typ
Power Supply Rejection (PSR)
80
AIN = 1 V, 20 Hz Update Rate
dBs min
Normal Mode 50 Hz/60 Hz Rejection
2
On AIN
60
50 Hz/60 Hz
±1 Hz
dBs min
On REFIN
60
50 Hz/60 Hz
±1 Hz, 20 Hz Update Rate
dBs min
DAC PERFORMANCE
DC Specifications
7
Resolution
12
Bits
Relative Accuracy
±3
LSB typ
Differential Nonlinearity
–1
Guaranteed 12-Bit Monotonic
LSB max
Offset Error
±50
mV max
Gain Error
8
±1AVDD Range
% max
±1VREF Range
% typ
AC Specifications2, 7
Voltage Output Settling Time
15
Settling Time to 1 LSB of Final Value
s typ
Digital-to-Analog Glitch Energy
10
1 LSB Change at Major Carry
nVs typ
(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V;
REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications TMIN to TMAX
unless otherwise noted.)
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