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參數(shù)資料
| 型號： | ADUC824BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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REV. B
ADuC824
–50–
I
2C-COMPATIBLE INTERFACE
The ADuC824 supports a 2-wire serial interface mode which is
I
2C compatible. The I2C-compatible interface shares its pins
with the on-chip SPI interface and therefore the user can only
enable one or the other interface at any given time (see SPE in
I2CADD
I
2C Address Register
Function
Holds the I
2C peripheral address for
the part. It may be overwritten by
user code. Technical Note uC001 at
describes the format of the I
2C stan-
dard 7-bit address in detail.
SFR Address
9BH
Power-On Default Value
55H
Bit Addressable
No
I2CDAT
I
2C Data Register
Function
The I2CDAT SFR is written by the
user to transmit data over the I
2C
interface or read by user code to read
data just received by the I
2C interface
Accessing I2CDAT automatically
clears any pending I
2C interrupt and
the I2CI bit in the I2CCON SFR.
User software should only access
I2CDAT once per interrupt cycle.
SFR Address
9AH
Power-On Default Value
00H
Bit Addressable
No
SPICON previously). An Application Note describing the
operation of this interface as implemented is available from
the MicroConverter Website at www.analog.com/microconverter.
This interface can be configured as a Software Master or Hard-
ware Slave, and uses two pins in the interface.
SDATA (Pin 27)
Serial Data I/O Pin
SCLOCK (Pin 26)
Serial Clock
Three SFRs are used to control the I2C-compatible interface. These are described below:
I2CCON
I
2C Control Register
SFR Address
E8H
Power-On Default Value
00H
Bit Addressable
Yes
O
D
ME
D
MO
C
MI
D
MM
C
2
IS
R
C
2
IX
T
C
2
II
C
2
I
Table XX. I2CCON SFR Bit Designations
Bit
Name
Description
7
MDO
I
2C Software Master Data Output Bit (MASTER MODE ONLY)
This data bit is used to implement a master I2C transmitter interface in software. Data written to this
bit will be outputted on the SDATA pin if the data output enable (MDE) bit is set.
6
MDE
I
2C Software Master Data Output Enable Bit (MASTER MODE ONLY)
Set by user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable SDATA pin as an input (Rx).
5
MCO
I
2C Software Master Clock Output Bit (MASTER MODE ONLY)
This data bit is used to implement a master I2C transmitter interface in software. Data written to
this bit will be outputted on the SCLOCK pin.
4
MDI
I
2C Software Master Data Input Bit (MASTER MODE ONLY)
This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA
pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) bit is ‘0.’
3
I2CM
I
2C Master/Slave Mode Bit
Set by user to enable I2C software master mode.
Cleared by user to enable I
2C hardware slave mode.
2
I2CRS
I
2C Reset Bit (SLAVE MODE ONLY)
Set by user to reset the I2C interface.
Cleared by user code for normal I
2C operation.
1
I2CTX
I
2C Direction Transfer Bit (SLAVE MODE ONLY)
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
0
I2CI
I
2C Interrupt Bit (SLAVE MODE ONLY)
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below).
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