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參數(shù)資料
| 型號(hào)： | ADUC824 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU |
| 中文描述： | MicroConverter的，雙通道ADC的16-/24-Bit與嵌入式閃存MCU |
| 文件頁(yè)數(shù)： | 42/68頁(yè) |
| 文件大?。?/td> | 1060K |
| 代理商： | ADUC824 |
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REV. B
ADuC824
–42–
ON-CHIP PLL
The ADuC824 is intended for use with a 32.768kHz watch crys-
tal. A PLL locks onto a multiple (384) of this to provide a stable
12.582912 MHz clock for the system. The core can operate at
this frequency or at binary submultiples of it to allow power
saving in cases where maximum core performance is not
required. The default core clock is the PLL clock divided by
8 or 1.572864 MHz. The ADC clocks are also derived from the
PLL clock, with the modulator rate being the same as the crystal
oscillator frequency. The above choice of frequencies ensures
that the modulators and the core will be synchronous, regardless
of the core clock rate. The PLL control register is PLLCON.
PLLCON
SFR Address
Power-On Default Value
Bit Addressable
PLL Control Register
D7H
03H
No
Table XV. PLLCON SFR Bit Designations
Bit
Name
Description
7
OSC_PD
Oscillator Power-down Bit
Set
by user to halt the 32 kHz oscillator in power-down mode.
Cleared
by user to enable the 32 kHz oscillator in power-down mode.
This feature allows the TIC to continue counting even in power-down mode.
PLL Lock Bit
This is a read only bit.
Set
automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. If the
external crystal becomes subsequently disconnected the PLL will rail and the core will halt.
Cleared
automatically at power-on to indicate the PLL is not correctly tracking the crystal clock.
This may be due to the absence of a crystal clock or an external crystal at power-on. In this mode,
the PLL output can be 12.58 MHz
±
20%.
Reserved for future use; should be written with ‘0.’
Reading this bit returns the state of the external
EA
pin latched at reset or power-on.
Fast Interrupt Response Bit
Set
by user enabling the response to any interrupt to be executed at the fastest core clock frequency,
regardless of the configuration of the CD2–0 bits (see below). Once user code has returned from an
interrupt, the core resumes code execution at the core clock selected by the CD2–0 bits.
Cleared
by user to disable the fast interrupt response feature.
CPU (Core Clock) Divider Bits
This number determines the frequency at which the microcontroller core will operate.
CD2
CD1
CD0
Core Clock Frequency (MHz)
0
0
0
12.582912
0
0
1
6.291456
0
1
0
3.145728
0
1
1
1.572864 (Default Core Clock Frequency)
1
0
0
0.786432
1
0
1
0.393216
1
1
0
0.196608
1
1
1
0.098304
6
LOCK
5
4
3
—
LTEA
FINT
2
1
0
CD2
CD1
CD0
OSC_PD
LOCK
—
LTEA
FINT
CD2
CD1
CD0
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PDF描述 |
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| ADUC824BS | MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC824BCP | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 8KB Flash 3.3V/5V 56-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 8KB FLASH 12.58MHZ 3.3/5V 56LFCSP - Bulk |
| ADUC824BCP-REEL | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 8KB Flash 3.3V/5V 56-Pin LFCSP EP T/R |
| ADUC824BCPZ | 功能描述:IC MCU 8K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:4KB（4K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC824BS | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 8KB Flash 3.3V/5V 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 8KB FLASH 12.58MHZ 3.3/5V 52MQFP - Bulk 制造商:Analog Devices 功能描述:8BIT MCU +24BIT ADC LQFP52 824 |
| ADUC824BS-DEN | 制造商:Analog Devices 功能描述: |
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