參數(shù)資料
型號: ADUC824
廠商: Analog Devices, Inc.
元件分類: 串行ADC
英文描述: MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU
中文描述: MicroConverter的,雙通道ADC的16-/24-Bit與嵌入式閃存MCU
文件頁數(shù): 31/68頁
文件大?。?/td> 1060K
代理商: ADUC824
REV. B
ADuC824
–31–
PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION
Overview
The ADuC824 incorporates two independent sigma-delta ADCs
(Primary and Auxiliary) with on-chip digital filtering intended
for the measurement of wide dynamic range, low frequency
signals, such as those in weigh-scale, strain-gauge, pressure trans-
ducer or temperature measurement applications.
Primary ADC
This ADC is intended to convert the primary sensor input. The
input is buffered and can be programmed for one of 8 input ranges
from
±
20 mV to
±
2.56 V, being driven from one of three differ-
ential input channel options AIN1/2, AIN3/4, or AIN3/2. The
input channel is internally buffered allowing the part to handle
significant source impedances on the analog input, allowing R/C
filtering (for noise rejection or RFI reduction) to be placed on
MODULATOR
PRODIGITAL
FILTER
SIGMA-DELTA A/D CONVERTER
BUFFER
AGND
AV
DD
REFIN(
) REFIN(+)
PROGAMPLIFIER
GTHE PROGRAMMABLE
2.56V (EXT VREF = 2.5V)
A HIGH-FREQUENCY 1-BIT
DTO THE DIGITAL FILTER,
THE DUTY CYCLE OF WHICH
RANALOG INPUT VOLTAGE
MODULATOR
CHOP
ANALOG INPUT CHOPPING
ALTTHROUGH THE
CCHOPPING YIELDS
EXCELLENT ADC OFFSET
APERFORMANCE
OUTPUT AVERAGE
AIMPLEMENTATION, EACH
DATA WORD OUTPUT
WITH ITS PREDECESSOR
TO OFFSET ERRORS
AIN1
AIN2
AIN3
AIN4
BUFFER AMPLIFIER
THE BUFFER AMPLIFIER
IALLOWING SIGNIFICANT
EXTERNAL SOURCE
IMPEDANCES
BURNOUT CURRENTS
TWO 100nA BURNOUT
USER TO EASILY DETECT
IF A OPEN-CIRCUIT
DIGITAL FILTER
BY THE MODULATOR. THE UPDATE
RATE AND BANDWIDTH OF THIS
FILTERVIA THE SF SFR
THE OUPUT WORD FROM THE
DIGITAL FILTER IS SCALED BY
CBEING PROVIDED AS
THE CONVERSION RESULT
OUTPUT SCALING
ANALOG MULTIPLEXER
FULLA DIFFERENTIAL MULTIPLEXER
AD(AIN2
AIN2).THE MULTIPLEXER IS
CSELECTION BITS IN ADC0CON
SIGMA-DELTA ADC
ARTHE SIGMA-DELTA
24 BITS NO MISSING
CODRIFT ERROR
OUTPUT
OUTPUT
DIGTAL OUTPUT
TO SFRs
PGA
REFERENCE
TINPUT TO THE ADuC824 IS
DIFFERENTIAL AND
FREFERENCE VOLTAGE IS
SELECTIN ADC0CON.
REFERENCE DETECT
SHORTED REFERENCES INPUTS
CHOP
MUX
SEE PAGE 36
SEE PAGES 29 AND 34
SEE PAGE 34
SEE PAGE 35
SEE PAGE 35
SEE PAGE 36
SEE PAGE 37
SEE PAGE 35
SEE PAGE 35
SEE PAGE 33
SEE PAGES 27 AND 33
Figure 18. Primary ADC Block Diagram
the analog inputs if required. On-chip burnout currents can
also be turned on. These currents can be used to check that a
transducer on the selected channel is still operational before
attempting to take measurements.
The ADC employs a sigma-delta conversion technique to realize
up to 24 bits of no missing codes performance. The sigma-delta
modulator converts the sampled input signal into a digital pulse
train whose duty cycle contains the digital information. A Sinc3
programmable low-pass filter is then employed to decimate the
modulator output data stream to give a valid data conversion
result at programmable output rates from 5.35 Hz (186.77 ms)
to 105.03 Hz (9.52 ms). A Chopping scheme is also employed
to minimize ADC offset errors. A block diagram of the Primary
ADC is shown in Figure 18.
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