參數(shù)資料
型號: ADUC824
廠商: Analog Devices, Inc.
元件分類: 串行ADC
英文描述: MicroConverter, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU
中文描述: MicroConverter的,雙通道ADC的16-/24-Bit與嵌入式閃存MCU
文件頁數(shù): 15/68頁
文件大?。?/td> 1060K
代理商: ADUC824
REV. B
–15–
ADuC824
Parameter
Min
Typ
Max
Unit
Figure
SPI MASTER MODE TIMING (CPHA = 0)
t
SL
SCLOCK Low Pulsewidth
*
t
SH
SCLOCK High Pulsewidth
*
t
DAV
Data Output Valid after SCLOCK Edge
t
DOSU
Data Output Setup before SCLOCK Edge
t
DSU
Data Input Setup Time before SCLOCK Edge
t
DHD
Data Input Hold Time after SCLOCK Edge
t
DF
Data Output Fall Time
t
DR
Data Output Rise Time
t
SR
SCLOCK Rise Time
t
SF
SCLOCK Fall Time
630
630
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
9
9
9
9
9
9
9
9
9
50
150
100
100
10
10
10
10
25
25
25
25
*
Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz and
b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively.
SCLOCK
(CPOL = 0)
t
DSU
SCLOCK
(CPOL = 1)
MOSI
MISO
MSB
LSB
LSB IN
BITS 6
1
BITS 6
1
MSB IN
t
DHD
t
DR
t
DAV
t
DF
t
DOSU
t
SH
t
SL
t
SR
t
SF
Figure 9. SPI Master Mode Timing (CPHA = 0)
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