Table XIX. SPICON SFR Bit Designations (continued) Bit Name Description 1 SPR1 SPI Bit-Rate Select Bits. 0 SPR0 These bits " />
參數(shù)資料
型號(hào)： ADUC816BSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 44/68頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8K FLASH ADC/DAC 52MQFP
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 7x16b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 738 (CN2011-ZH PDF)
REV. 0
ADuC816
–49–
Table XIX. SPICON SFR Bit Designations (continued)
Bit
Name
Description
1
SPR1
SPI Bit-Rate Select Bits.
0
SPR0
These bits select the SCLOCK rate (bit-rate) in Master Mode as follows:
SPR1
SPR0
Selected Bit Rate
00fCORE/2
01fCORE/4
10fCORE/8
11fCORE/16
In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external
SS pin (Pin 13), can be read
via the SPR0 bit.
NOTE
The CPOL and CPHA bits should both contain the same values for master and slave devices.
SPIDAT
SPI Data Register
Function
The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user
code to read data just received by the SPI interface.
SFR Address
F7H
Power-On Default Value
00H
Bit Addressable
No
Using the SPI Interface
Depending on the configuration of the bits in the SPICON SFR
shown in Table XIX, the ADuC816 SPI interface will transmit
or receive data in a number of possible modes. Figure 32 shows
all possible ADuC816 SPI configurations and the timing rela-
tionships and synchronization between the signals involved.
Also shown in this figure is the SPI interrupt bit (ISPI) and how
it is triggered at the end of each byte-wide communication.
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
ISPI FLAG
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
?
MSB
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
SS
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
Figure 32. SPI Timing, All Modes
SPI Interface—Master Mode
In master mode, the SCLOCK pin is always an output and gener-
ates a burst of eight clocks whenever user code writes to the
SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. It should also be noted that the
SS pin is not used in master mode. If the ADuC816 needs to
assert the
SS pin on an external slave device, a Port digital output
pin should be used.
In master mode a byte transmission or reception is initiated
by a write to SPIDAT. Eight clock periods are generated via the
SCLOCK pin and the SPIDAT byte being transmitted via MOSI.
With each SCLOCK period a data bit is also sampled via MISO.
After eight clocks, the transmitted byte will have been completely
transmitted and the input byte will be waiting in the input shift
register. The ISPI flag will be set automatically and an interrupt
will occur if enabled. The value in the shift register will be latched
into SPIDAT.
SPI Interface—Slave Mode
In slave mode the SCLOCK is an input. The
SS pin must
also be driven low externally during the byte communication.
Transmission is also initiated by a write to SPIDAT. In slave
mode, a data bit is transmitted via MISO and a data bit is received
via MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte will have been completely transmitted and the
input byte will be waiting in the input shift register. The ISPI flag
will be set automatically and an interrupt will occur if enabled.
The value in the shift register will be latched into SPIDAT only
when the transmission/reception of a byte has been completed.
The end of transmission occurs after the eighth clock has been
received, if CPHA = 1 or when
SS returns high if CPHA = 0.
REV. A
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