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參數(shù)資料
| 型號(hào)： | ADUC816BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 43/68頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 52MQFP |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 7x16b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 738 (CN2011-ZH PDF) |
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REV. 0
ADuC816
–48–
SERIAL PERIPHERAL INTERFACE
The ADuC816 integrates a complete hardware Serial Peripheral
Interface (SPI) interface on-chip. SPI is an industry standard syn-
chronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously, i.e., full
duplex. It should be noted that the SPI physical interface is shared
with the I
2C interface and therefore the user can only enable one
or the other interface at any given time (see SPE in SPICON
below). The system can be configured for Master or Slave opera-
tion and typically consists of four pins, namely:
MISO (Master In, Slave Out Data I/O Pin), Pin 14
The MISO (master in slave out) pin is configured as an input line
in master mode and an output line in slave mode. The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out). The data is transferred as
byte wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin), Pin 27
The MOSI (master out slave in) pin is configured as an output line
in master mode and an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SCLOCK (Serial Clock I/O Pin), Pin 26
The master clock (SCLOCK) is used to synchronize the data
being transmitted and received through the MOSI and MISO
data lines. A single data bit is transmitted and received in
each SCLOCK period. Therefore, a byte is transmitted/received
after eight SCLOCK periods. The SCLOCK pin is configured
as an output in master mode and as an input in slave mode. In
master mode the bit-rate, polarity and phase of the clock are
controlled by the CPOL, CPHA, SPR0 and SPR1 bits in the
SPICON SFR (see Table XIX below). In slave mode the
SPICON register will have to be configured with the phase and
polarity (CPHA and CPOL) of the expected input clock. In
both master and slave mode the data is transmitted on one edge
of the SCLOCK signal and sampled on the other. It is important
therefore that the CPHA and CPOL are configured the same for the
master and slave devices.
SS (Slave Select Input Pin), Pin 13
The Slave Select (
SS) input pin is only used when the ADuC816
is configured in slave mode to enable the SPI peripheral. This line
is active low. Data is only received or transmitted in slave mode
when the
SS pin is low, allowing the ADuC816 to be used in single
master, multislave SPI configurations. If CPHA = 1 then the
SS
input may be permanently pulled low. With CPHA = 0 then the
SS input must be driven low before the first bit in a byte wide
transmission or reception and return high again after the last bit
in that byte wide transmission or reception. In SPI Slave Mode,
the logic level on the external
SS pin (Pin 13), can be read via
the SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
SPICON:
SPI Control Register
SFR Address
F8H
Power-On Default Value
04H
Bit Addressable
Yes
I
P
S
IL
O
C
WE
P
SM
I
P
SL
O
P
CA
H
P
C1
R
P
S0
R
P
S
Table XIX. SPICON SFR Bit Designations
Bit
Name
Description
7
ISPI
SPI Interrupt Bit.
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR
6
WCOL
Write Collision Error Bit.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
5
SPE
SPI Interface Enable Bit.
Set by user to enable the SPI interface.
Cleared by user to enable the I
2C interface.
4
SPIM
SPI Master/Slave Mode Select Bit.
Set by user to enable Master Mode operation (SCLOCK is an output).
Cleared by user to enable Slave Mode operation (SCLOCK is an input).
3
CPOL
Clock Polarity Select Bit.
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
2
CPHA
Clock Phase Select Bit.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
REV. A
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