Serial Safe Mode This mode disables serial download capability on the device. If Serial Safe mode is activated and an attem" />
參數(shù)資料
型號(hào)： ADUC816BCP
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/68頁(yè)
文件大小： 0K
描述： IC MCU 8K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 7x16b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 738 (CN2011-ZH PDF)
REV. 0
ADuC816
–39–
Serial Safe Mode
This mode disables serial download capability on the device. If
Serial Safe mode is activated and an attempt is made to reset
the part into serial download mode, i.e., RESET asserted and
deasserted with
PSEN low, the part will interpret the serial
download reset as a normal reset only. It will, therefore, not
enter serial download mode but only execute a normal reset
sequence. Serial Safe mode can only be disabled by initiating a
code-erase command in parallel programming mode.
Using the Flash/EE Data Memory
The user Flash/EE data memory array consists of 640 bytes that
are configured into 160 (00H to 9FH) 4-byte pages as shown in
Figure 29.
9FH
BYTE 1
BYTE 2
BYTE 3
BYTE 4
00H
BYTE 1
BYTE 2
BYTE 3
BYTE 4
Figure 29. Flash/EE Data Memory Configuration
As with other ADuC816 user-peripheral circuits, the interface to
this memory space is via a group of registers mapped in the SFR
space. A group of four data registers (EDATA1–4) are used to
hold 4-byte page data just accessed. EADRL is used to hold the
8-bit address of the page to be accessed. Finally, ECON is an 8-
bit control register that may be written with one of five Flash/EE
memory access commands to trigger various read, write, erase, and
verify functions. These registers can be summarized as follows:
ECON:
SFR Address:
B9H
Function:
Controls access to 640 Bytes
Flash/EE Data Space.
Default:
00H
EADRL:
SFR Address:
C6H
Function:
Holds the Flash/EE Data Page
Address. (640 Bytes => 160 Page
Addresses.)
Default:
00H
EDATA 1–4:
SFR Address:
BCH to BFH respectively
Function:
Holds Flash/EE Data memory
page write or page read data bytes.
Default :
EDATA1–2 –> 00H
EDATA3–4 –> 00H
A block diagram of the SFR interface to the Flash/EE Data
Memory array is shown in Figure 30.
9FH
BYTE 1 BYTE 2 BYTE 3 BYTE 4
00H
EDATA1 (BYTE 1)
EDATA2 (BYTE 2)
EDATA3 (BYTE 3)
EDATA4 (BYTE 4)
EADRL
ECON COMMAND
INTERPRETER LOGIC
ECON
BYTE 1 BYTE 2 BYTE 3 BYTE 4
FUNCTION:
RECEIVES COMMAND DATA
FUNCTION:
HOLDS THE 8-BIT PAGE
ADDRESS POINTER
FUNCTION:
INTERPRETS THE FLASH
COMMAND WORD
FUNCTION:
HOLDS THE 4-BYTE
PAGE DATA
Figure 30. Flash/EE Data Memory Control and Configuration
ECON—Flash/EE Memory Control SFR
This SFR acts as a command interpreter and may be written with
one of five command modes to enable various read, program and
erase cycles as detailed in Table XIII:
Table XIII. ECON–Flash/EE Memory Control Register
Command Modes
Command
Byte
Command Mode
01H
READ COMMAND.
Results in four bytes being read into EDATA1–4
from memory page address contained in EADRL.
02H
PROGRAM COMMAND.
Results in four bytes (EDATA1–4) being written
to memory page address in EADRL. This write
command assumes the designated “write” page has
been pre-erased.
03H
RESERVED FOR INTERNAL USE.
03H should not be written to the ECON SFR.
04H
VERIFY COMMAND.
Allows the user to verify if data in EDATA1–4 is
contained in page address designated by EADRL.
A subsequent read of the ECON SFR will result
in a “zero” being read if the verification is valid,
a nonzero value will be read to indicate an invalid
verification.
05H
ERASE COMMAND.
Results in an erase of the 4-byte page designated
in EADRL.
06H
ERASE-ALL COMMAND.
Results in erase of the full Flash/EE Data memory
160-page (640 bytes) array.
07H to FFH
RESERVED COMMANDS.
Commands reserved for future use.
REV. A
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