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參數(shù)資料
| 型號： | ADUC816BCP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 7x16b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
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REV. 0
ADuC816
–35–
mended. Deriving the reference input voltage across an external
resistor, as shown in Figure 52, will mean that the reference
input sees a significant external source impedance. External
decoupling on the REFIN(+) and REFIN(–) pins would not be
recommended in this type of circuit configuration.
Reference Detect
The ADuC816 includes on-chip circuitry to detect if the part has a
valid reference for conversions or calibrations. If the voltage
between the external REFIN(+) and REFIN(–) pins goes below
0.3 V or either the REFIN(+) or REFIN(–) inputs is open circuit,
the ADuC816 detects that it no longer has a valid reference. In
this case, the NOXREF bit of the ADCSTAT SFR is set to a 1. If
the ADuC816 is performing normal conversions and the NOXREF
bit becomes active, the conversion results revert to all 1s. Therefore,
it is not necessary to continuously monitor the status of the
NOXREF bit when performing conversions. It is only necessary
to verify its status if the conversion result read from the ADC Data
Register is all 1s.
If the ADuC816 is performing either an offset or gain calibration
and the NOXREF bit becomes active, the updating of the respec-
tive calibration registers is inhibited to avoid loading incorrect
coefficients to these registers, and the appropriate ERR0 or ERR1
bits in the ADCSTAT SFR are set. If the user is concerned
about verifying that a valid reference is in place every time a cali-
bration is performed, the status of the ERR0 or ERR1 bit should
be checked at the end of the calibration cycle.
Sigma-Delta Modulator
A sigma-delta ADC generally consists of two main blocks, an
analog modulator and a digital filter. In the case of the ADuC816
ADCs, the analog modulators consist of a difference amplifier,
an integrator block, a comparator, and a feedback DAC as illus-
trated in Figure 20.
DAC
INTEGRATOR
ANALOG
INPUT
DIFFERENCE
AMP
COMPARATOR
HIGH-
FREQUENCY
BITSTREAM
TO DIGITAL
FILTER
Figure 20. Sigma-Delta Modulator Simplified Block Diagram
In operation, the analog signal sample is fed to the difference
amplifier along with the output of the feedback DAC. The differ-
ence between these two signals is integrated and fed to the
comparator. The output of the comparator provides the input to
the feedback DAC so the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the comparator.
This duty cycle data can be recovered as a data word using a
subsequent digital filter stage. The sampling frequency of
the modulator loop is many times higher than the bandwidth of
the input signal. The integrator in the modulator shapes the
quantization noise (which results from the analog-to-digital con-
version) so that the noise is pushed toward one-half of the
modulator frequency.
Digital Filter
The output of the sigma-delta modulator feeds directly into the
digital filter. The digital filter then band-limits the response to a
frequency significantly lower than one-half of the modulator
frequency. In this manner, the 1-bit output of the comparator
is translated into a band-limited, low noise output from the
ADuC816 ADCs.
The ADuC816 filter is a low-pass, Sinc
3 or (sinx/x)3 filter whose
primary function is to remove the quantization noise introduced
at the modulator. The cutoff frequency and decimated output data
rate of the filter are programmable via the SF (Sinc Filter) SFR
as described in Table VII.
Figure 21 shows the frequency response of the ADC chan-
nel at the default SF word of 69 dec or 45 hex, yielding an
overall output update rate of just under 20 Hz.
It should be noted that this frequency response allows frequency
components higher than the ADC Nyquist frequency to pass
through the ADC, in some cases without significant attenuation.
These components may, therefore, be aliased and appear in-band
after the sampling process.
It should also be noted that rejection of mains-related frequency
components, i.e., 50 Hz and 60 Hz, is seen to be at level of
>65 dB at 50 Hz and >100 dB at 60 Hz. This confirms the
data sheet specifications for 50 Hz/60 Hz Normal Mode Rejec-
tion (NMR) at a 20 Hz update rate.
0
20
30
50
70
80
90
100
110
FREQUENCY – Hz
GAIN
–
dB
0
–20
–40
–70
–80
–90
–100
–110
–120
10
40
60
–10
–30
–60
–50
Figure 21. Filter Response, SF = 69 dec
The response of the filter, however, will change with SF word as
can be seen in Figure 22, which shows >90 dB NMR at 50 Hz
and >70 dB NMR at 60 Hz when SF = 255 dec.
020
30
50
70
80
90
100
FREQUENCY – Hz
GAIN
–
dB
0
–20
–40
–70
–80
–90
–100
–110
–120
10
40
60
–10
–30
–60
–50
Figure 22. Filter Response, SF = 255 dec
REV. A
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