參數(shù)資料
型號(hào): ADUC816BCP
廠商: Analog Devices Inc
文件頁數(shù): 11/68頁
文件大?。?/td> 0K
描述: IC MCU 8K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 12.58MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: PSM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 7x16b; D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
包裝: 托盤
產(chǎn)品目錄頁面: 738 (CN2011-ZH PDF)
ADuC816
PIN FUNCTION DESCRIPTIONS
PIN 1
ADuC816
TOP VIEW
(Not to Scale)
00
43
6-
00
1
1
14
13
26
27
40
39
52
PIN 1
INDICATOR
1
14
42
29
NOTES
1. THE EXPOSED PADDLE MUST BE LEFT
UNCONNECTED.
15
28
43
TOP VIEW
(Not to Scale)
ADuC816
56
00
43
6-
0
02
56-Lead MQFP
56-Lead LFCSP
PIN FUNCTION DESCRIPTIONS
Pin No.
52-Lead
MQFP
Pin No.
56-Lead
CSP
Mnemonic
Type1
Description
1, 2
56, 1
P1.0/P1.1
I/O
P1.0 and P1.1 can function as digital inputs or digital outputs and have a pull-up configuration as
described for Port 3. P1.0 and P1.1 have an increased current drive sink capability of 10 mA.
P1.0/T2
I/O
P1.0 and P1.1 also have various secondary functions as described below. P1.0 can be used to
provide a clock input to Timer 2. When enabled, Counter 2 is incremented in response to a
negative transition on the T2 input pin.
P1.1/T2EX
I/O
P1.1 can also be used to provide a control input to Timer 2.When enabled, a negative transition
on the T2EX input pin will cause a Timer 2 capture or reload event.
3–4,
2–3,
P1.2–P1.7
I
Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital input
9–12
11–14
P1.2/DAC/IEXC1
I/O
for which 0 must be written to the port bit. As a digital input, these pins must be driven high or
low externally. These pins also have the following analog functionality: The voltage output from
the DAC or one or both current sources (200 μA or 2 × 200 μA) can be configured to appear at
this pin.
P1.3/AIN5/IEXC2
I/O
Auxiliary ADC input or one or both current sources can be configured at this pin.
P1.4/AIN1
I
Primary ADC, Positive Analog Input
P1.5/AIN2
I
Primary ADC, Negative Analog Input
P1.6/AIN3
I
Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input
P1.7/AIN4/DAC
I/O
Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The voltage output from the
DAC can also be configured to appear at this pin.
5
4, 5
AVDD
S
Analog Supply Voltage, 3 V or 5 V
6
6, 7, 8
AGND
S
Analog Ground. Ground reference pin for the analog circuitry.
7
9
REFIN(–)
I
Reference Input, Negative Terminal
8
10
REFIN(+)
I
Reference Input, Positive Terminal
13
15
SS
I
Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.
14
16
MISO
I/O
Master Input/Slave Output for the SPI Interface. A weak pull-up is present on this input pin
15
17
RESET
I
Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is running resets
the device. There is an internal weak pull-down and a Schmitt trigger input stage on this pin.
16–19,
18–21,
P3.0–P3.7
I/O
P3.0–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins that
22–25
24–27
P3.0/RXD
I/O
have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be
used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of
the internal pull-up resistors.When driving a 0-to-1 output transition, a strong pull-up is active for
two core clock periods of the instruction cycle. Port 3 pins also have various secondary functions
including: Receiver Data for UART Serial Port
P3.1/TXD
I/O
Transmitter Data for UART Serial Port
P3.2/INT0
I/O
External Interrupt 0.This pin can also be used as a gate control input to Timer 0.
P3.3/INT1
I/O
External Interrupt 1.This pin can also be used as a gate control input to Timer 1.
P3.4/T0
I/O
Timer/Counter 0 External Input.
P3.5/T1
I/O
Timer/Counter 1 External Input
P3.6/WR
I/O
External Data Memory Write Strobe. Latches the data byte from Port 0 into an external data
memory.
P3.7/RD
I/O
External Data Memory Read Strobe. Enables the data from an external data memory to Port 0.
REV. A
–19–
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