參數(shù)資料
型號(hào)： ADUC7128BCPZ126-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 65/92頁(yè)
文件大?。?/td> 0K
描述： IC DAS MCU ARM7 ADC/DDS 64-LFCSP
產(chǎn)品培訓(xùn)模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PLA，POR，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 28
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 64-LFQFN 裸露焊盤(pán)，CSP
包裝： 標(biāo)準(zhǔn)包裝
配用： EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128
其它名稱： ADUC7128BCPZ126-RLDKR
ADuC7128/ADuC7129
Rev. 0 | Page 68 of 92
Bit
Description
7
Master Serial Clock Enable Bit.
Set by user to enable generation of the serial clock in master mode.
Cleared by user to disable serial clock in master mode.
6
Loop-Back Enable Bit.
Set by user to internally connect the transition to the reception to test user software.
Cleared by user to operate in normal mode.
5
Start Back-Off Disable Bit.
Set by user in multimaster mode. If losing arbitration, the master immediately tries to retransmit.
Cleared by user to enable start back-off. After losing arbitration, the master waits before trying to retransmit.
4
Hardware General Call Enable. When this bit and Bit 3 are set, and have received a general call (Address 0x00) and a data byte, the
device checks the contents of the I2C0ALT against the receive register. If the contents match, the device has received a hardware
general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to.
This is a “to whom it may concern” call. The ADuC7128/ADuC7129 watch for these addresses. The device that requires attention
embeds its own address into the message. All masters listen and the one that can handle the device contacts its slave and acts
appropriately. The LSB of the I2C0ALT register should always be written to a 1, as per the I2C January 2000 specification.
3
General Call Enable Bit.
Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data
bit. If it receives a 0x06 (reset and write programmable part of slave address by hardware) as the data byte, the I2C interface resets as per
the I2C January 2000 specification. This command can be used to reset an entire I2C system. The general call interrupt status bit
sets on any general call. The user must take corrective action by setting up the I2C interface after a reset. If it receives a 0x04
(write programmable part of slave address by hardware) as the data byte, the general call interrupt status bit sets on any general
call. The user must take corrective action by reprogramming the device address.
2
Reserved.
1
Master Enable Bit.
Set by user to enable the master I2C channel.
Cleared by user to disable the master I2C channel.
0
Slave Enable Bit.
Set by user to enable the slave I2C channel. A slave transfer sequence is monitored for the device address in I2C0ID0, I2C0ID1,
I2C0ID2, and I2C0ID3. If the device address is recognized, the part participates in the slave transfer sequence.
Cleared by user to disable the slave I2C channel.
I2CxDIV Register
Name
Address
Default Value
Access
I2C0DIV
0xFFFF0830
0x1F1F
R/W
I2C1DIV
0xFFFF0930
0x1F1F
R/W
I2CxDIV are the clock divider registers.
I2CxIDx Register
Name
Address
Default Value
Access
I2C0ID0
0xFFFF0838
0x00
R/W
I2C0ID1
0xFFFF083C
0x00
R/W
I2C0ID2
0xFFFF0840
0x00
R/W
I2C0ID3
0xFFFF0844
0x00
R/W
I2C1ID0
0xFFFF0938
0x00
R/W
I2C1ID1
0xFFFF093C
0x00
R/W
I2C1ID2
0xFFFF0940
0x00
R/W
I2C1ID3
0xFFFF0944
0x00
R/W
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address
device ID registers of I2Cx.
I2CxSSC Register
Name
Address
Default Value
Access
I2C0SSC
0xFFFF0848
0x01
R/W
I2C1SSC
0xFFFF0948
0x01
R/W
I2CxSSC is an 8-bit start/stop generation counter. It holds off
SDA low for start and stop conditions.
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