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| 型號： | ADUC7128BCPZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/92頁 |
| 文件大小： | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 64-LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 28 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 64-LFQFN 裸露焊盤，CSP |
| 包裝： | 標準包裝 |
| 配用： | EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128 |
| 其它名稱： | ADUC7128BCPZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 39 of 92
NONVOLATILE FLASH/EE MEMORY
FLASH/EE MEMORY OVERVIEW
The ADuC7128/ADuC7129 incorporate Flash/EE memory
technology on-chip to provide the user with nonvolatile, in-
circuit reprogrammable memory space.
Like EEPROM, Flash memory can be programmed in-system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, Flash memory is often,
and more correctly, referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC7128/ADuC7129, Flash/EE memory technology
allows the user to update program code space in-circuit,
without the need to replace one-time programmable (OTP)
devices at remote operating nodes.
FLASH/EE MEMORY
The ADuC7128/ADuC7129 contain two 64 kB arrays of
Flash/EE memory. In the first block, the lower 62 kB are
available to the user and the upper 2 kB of this Flash/EE
program memory array contain permanently embedded
firmware, allowing in-circuit serial download. The 2 kB of
embedded firmware also contain a power-on configuration
routine that downloads factory calibrated coefficients to the
various calibrated peripherals, such as band gap references.
This 2 kB embedded firmware is hidden from user code. It is not
possible for the user to read, write, or erase this page. In the second
block, all 64 kB of Flash/EE memory are available to the user.
The 126 kB of Flash/EE memory can be programmed in-circuit,
using the serial download mode or the JTAG mode provided.
Flash/EE Memory Reliability
The Flash/EE memory arrays on the parts are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
1.
Initial page erase sequence
2.
Read/verify, sequence a single Flash/EE location
3.
Byte program sequence memory
4.
Second read/verify sequence endurance cycle
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in
the Flash/EE memory is cycled 10,000 times from 0x0000
to 0xFFFF.
As indicated in Table 1 of the Specifications section, the
Flash/EE memory endurance qualification is carried out in
accordance with JEDEC Retention Lifetime Specification A117
over the industrial temperature range of –40° to +125°C. The
results allow the specification of a minimum endurance figure
over a supply temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. Note, too, that retention
lifetime, based on an activation energy of 0.6 eV, derates with
150
300
450
600
30
40
55
70
85
100
125
135
150
RE
T
E
NT
IO
N
(
Y
ea
rs
)
0
04
95
5-
08
5
JUNCTION TEMPERATURE (°C)
Figure 44. Flash/EE Memory Data Retention
Serial Downloading (In-Circuit Programming)
The ADuC7128/ADuC7129 facilitate code download via the
standard UART serial port. The ADuC7128/ADuC7129 enter
serial download mode after a reset or power cycle if the BM pin
is pulled low through an external 1 kΩ resistor. Once in serial
download mode, the user can download code to the full 126 kB
of Flash/EE memory while the device is in-circuit in its target appli-
cation hardware. A PC serial download executable is provided as
part of the development system for serial downloads via the UART.
For additional information, an application note is available at
www.analog.com/microconverter describing the protocol for
serial downloads via the UART.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to
facilitate code download and debug.
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