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參數(shù)資料
| 型號(hào)： | ADUC7061BCPZ32-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 96/108頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 16/32BIT 32KB 32LFCSP |
| 產(chǎn)品變化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 設(shè)計(jì)資源： | USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 10MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 8 |
| 程序存儲(chǔ)器容量： | 32KB（16K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.375 V ~ 2.625 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 5x24b，8x24b，D/A 1x14b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 88 of 108
Table 97. I2CMCON MMR Bit Designations
Bit
Name
Description
15:9
Reserved. These bits are reserved and should not be written to.
8
I2CMCENI
I2C transmission complete interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I2C bus.
Clear this interrupt source.
7
I2CNACKENI
I2C no acknowledge (NACK) received interrupt enable bit.
Set this bit to enable interrupts when the I2C master receives a no acknowledge.
Clear this interrupt source.
6
I2CALENI
I2C arbitration lost interrupt enable bit.
Set this bit to enable interrupts when the I2C master did not gain control of the I2C bus.
Clear this interrupt source.
5
I2CMTENI
I2C transmit interrupt enable bit.
Set this bit to enable interrupts when the I2C master has transmitted a byte.
Clear this interrupt source.
4
I2CMRENI
I2C receive interrupt enable bit.
Set this bit to enable interrupts when the I2C master receives data.
Cleared by user to disable interrupts when the I2C master is receiving data.
3
I2CMSEN
I2C master SCL stretch enable bit.
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
2
I2CILEN
I2C internal loopback enable.
Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their
respective input signals.
Cleared by user to disable loopback mode.
1
I2CBD
I2C master backoff disable bit.
Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start
condition.
Clear this bit to back off until the I2C bus becomes free.
0
I2CMEN
I2C master enable bit.
Set by user to enable the I2C master mode.
Cleared to disable the I2C master mode.
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