參數(shù)資料
型號： ADUC7061BCPZ32-RL
廠商： Analog Devices Inc
文件頁數(shù)： 36/108頁
文件大?。?/td> 0K
描述： IC MCU 16/32BIT 32KB 32LFCSP
產品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設計資源： USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075)
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
標準包裝： 5,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 8
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內部
工作溫度： -40°C ~ 125°C
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 33 of 108
RESET
There are four kinds of resets: external reset, power-on reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can be written by user
code to initiate a software reset event.
The bits in this register can be cleared to 0 by writing to the
RSTCLR MMR at 0xFFFF0234. The bit designations in
RSTCLR mirror those of RSTSTA. These registers can be used
during a reset exception service routine to identify the source of
the reset. The implications of all four kinds of reset events are
tabulated in Table 30.
RSTSTA Register
Name:
RSTSTA
Address:
0xFFFF0230
Default value: Depends on type of reset
Access:
Read and write
Function:
This 8-bit register indicates the source of the
last reset event and can be written by user code
to initiate a software reset.
RSTCLR Register
Name:
RSTCLR
Address:
0xFFFF0234
Access:
Write only
Function:
This 8-bit write only register clears the corres-
ponding bit in RSTSTA.
Table 29. RSTSTA/RSTCLR MMR Bit Designations
Bit
Description
7:4
Not used. These bits are not used and always
read as 0.
3
External reset.
Automatically set to 1 when an external reset
occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
2
Software reset.
This bit is set to 1 by user code to generate a soft-
ware reset.
This bit is cleared by setting the corresponding bit
in RSTCLR.1
1
Watchdog timeout.
Automatically set to 1 when a watchdog timeout
occurs.
Cleared by setting the corresponding bit in RSTCLR.
0
Power-on reset.
Automatically set when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
1
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
clear this bit generates a software reset.
Table 30. Device Reset Implications
RESET
Reset
External Pins to
Default State
Kernel
Executed
Reset All
External MMRs
(Excluding RSTSTA)
Peripherals
Reset
Watchdog
Timer Reset
RAM
Valid
RSTSTA
(Status After
Reset Event)
POR
Yes
Yes/No
RSTSTA[0] = 1
Watchdog
Yes
No
Yes
RSTSTA[1] = 1
Software
Yes
No
Yes
RSTSTA[2] = 1
External Pin
Yes
No
Yes
RSTSTA[3] = 1
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