參數(shù)資料
型號： ADUC7061BCPZ32-RL
廠商： Analog Devices Inc
文件頁數(shù)： 23/108頁
文件大小： 0K
描述： IC MCU 16/32BIT 32KB 32LFCSP
產(chǎn)品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設(shè)計(jì)資源： USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075)
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
標(biāo)準(zhǔn)包裝： 5,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 8
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 21 of 108
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit, reduced instruction set computer
(RISC), developed by ARM Ltd. The ARM7TDMI is a
von Neumann-based architecture, meaning that it uses a single
32-bit bus for instruction and data. The length of the data can
be 8, 16, or 32 bits, and the length of the instruction word is
either 16 bits or 32 bits, depending on the mode in which the
core is operating.
The ARM7TDMI is an ARM7 core with four additional
features, as listed in Table 10.
Table 10. ARM7TDMI Features
Feature
Description
T
Support for the Thumb (16-bit) instruction set
D
Support for debug
M
Enhanced multiplier
I
Includes the EmbeddedICE module to support
embedded system debugging
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set compressed into 16 bits, the
Thumb instruction set. Faster code execution from 16-bit memory
and greater code density is achieved by using the Thumb instruc-
tion set, making the ARM7TDMI core particularly suited for
embedded applications.
However, the Thumb mode has three limitations.
Relative to ARM, the Thumb code usually requires more
instructions to perform the same task. Therefore, ARM
code is best for maximizing the performance of time-
critical code in most applications.
The Thumb instruction set does not include some
instructions that are needed for exception handling, so
ARM code can be required for exception handling.
When an interrupt occurs, the core vectors to the interrupt
location in memory and executes the code present at that
address. The first command is required to be in ARM code.
MULTIPLIER (M)
The ARM7TDMI instruction set includes an enhanced
multiplier, with four extra instructions to perform 32-bit by
32-bit multiplication with a 64-bit result, and 32-bit by 32-bit
multiplication-accumulation (MAC) with a 64-bit result.
EmbeddedICE (I)
The EmbeddedICE module provides integrated on-chip debug
support for the ARM7TDMI. The EmbeddedICE module
contains the breakpoint and watchpoint registers that allow
nonintrusive user code debugging. These registers are con-
trolled through the JTAG test port. When a breakpoint or
watchpoint is encountered, the processor halts and enters the
debug state. When in a debug state, the processor registers can
be interrogated, as can the Flash/EE, SRAM, and memory
mapped registers.
ARM7 Exceptions
The ARM7 supports five types of exceptions, with a privileged
processing mode associated with each type. The five types of
exceptions are as follows:
Type 1: normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and external
events. Note that the ADuC706x supports eight configurable
priority levels for all IRQ sources.
Type 2: fast interrupt or FIQ. This is provided to service data
transfer or a communication channel with low latency. FIQ has
priority over IRQ. Note that the ADuC706x supports eight
configurable priority levels for all FIQ sources.
Type 3: memory abort (prefetch and data).
Type 4: attempted execution of an undefined instruction.
Type 5: software interrupts (SWI) instruction that can be used
to make a call to an operating system.
Typically, the programmer defines interrupts as IRQ, but for
higher priority interrupts, the programmer can define
interrupts as the FIQ type.
The priority of these exceptions and vector addresses are listed
Table 11. Exception Priorities and Vector Addresses
Priority
Exception
Address
1
Hardware reset
0x00
2
Memory abort (data)
0x10
3
FIQ
0x1C
4
IRQ
0x18
5
Memory abort (prefetch)
0x0C
6
Software interrupt1
0x08
6
Undefined instruction1
0x04
1
A software interrupt and an undefined instruction exception have the same
priority and are mutually exclusive.
The exceptions listed in Table 11 are located from 0x00 to 0x1C,
with a reserved location at 0x14.
ARM REGISTERS
The ARM7TDMI has 16 standard registers. R0 to R12 are for
data manipulation, R13 is the stack pointer, R14 is the link
register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched (when using the
branch and link command) or the command during which an
exception occurred.
The stack pointer contains the current location of the stack.
Generally, on an ARM7TDMI, the stack starts at the top of the
available RAM area and descends using the area as required. A
separate stack is defined for each of the exceptions. The size of
each stack is user configurable and is dependent on the target
application. When programming using high level languages,
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