參數(shù)資料
型號(hào)： ADSP-BF526KBCZ-4C2
廠商： Analog Devices Inc
文件頁數(shù)： 13/36頁
文件大小： 0K
描述： IC DSP CTRLR 400MHZ 289CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： DMA，以太網(wǎng)，I²C，PPI，SPI，SPORT，UART，USB
時(shí)鐘速率： 400MHz
非易失內(nèi)存： ROM（32 kB）
芯片上RAM： 132kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.30V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 289-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 289-CSPBGA（12x12）
包裝： 托盤
Rev. A
|
Page 20 of 36
|
March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Table 11. Register 7 Digital Audio I/F
Bit Name
Bits
Description
Settings
BCLKINV
B7
CODEC_BCLK inversion control
0 = CODEC_BCLK not inverted (default)
1 = CODEC_BCLK inverted
MS
B6
Master mode enable
0 = enable slave mode (default)
1 = enable master mode
LRSWAP
B5
Swap DAC data control
0 = output left- and right-channel data as normal (default)
1 = swap left- and right-channel DAC data in audio interface
LRP
B4
Polarity control for clocks in right-justified,
left-justified, and I2S modes
0 = normal DACLRC and ADCLRC (default),
or processor Submode 1
1 = invert DACLRC and ADCLRC polarity, or processor Submode 2
WL [1:0]
B[3:2] Data-word length control
00 = 16 bits
01 = 20 bits
10 = 24 bits (default)
11 = 32 bits
FORMAT [1:0]
B[1:0] Digital audio input format control
00 = right justified
01 = left justified
10 = I2S mode (default)
11 = processor mode
Table 12. Register 8 Sampling Rate
Bit Name
Bits
Description
Settings
CLKODIV2
B7
CODEC_CLKOUT divider select
0 = CODEC_CLKOUT is codec clock (default)
1 = CODEC_CLKOUT is codec clock divided by 2
CLKDIV2
B6
Codec clock divide select
0 = codec clock is CODEC_MCLK (default)
1= codec clock is CODEC_MCLK divided by 2
SR [3:0]
B[5:2]
Clock setting condition
BOSR
B1
Base oversampling rate
USB mode:
0 = support for 250 × fS based clock (default)
1 = support for 272 × fS based clock
Normal mode:
0 = support for 256 × fS based clock (default)
1 = support for 384 × fS based clock
USB
B0
USB mode select
0 = normal mode enable (default)
1 = USB mode enable
Table 13. Register 9 Active
Bit Name
Bit
Description
Settings
ACTIVE
B0
Digital core activation control
0 = disable digital core (default)
1 = activate digital core
Table 14. Register 10 Software Reset
Bit Name
Bit
Description
Settings
RESET [8:0] B[8:0] Write all 0s to this register to set all registers to their default settings.
Other data written to this register has no effect.
0 = reset (default)
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參數(shù)描述
ADSP-BF526KBCZ4C2X 制造商:Analog Devices 功能描述:DSP 32-BIT 400MHZ - Trays
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ADSP-BF526KBCZENGC2 制造商:Analog Devices 功能描述:
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