參數(shù)資料
型號(hào)： ADSP-21992YBC
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/60頁(yè)
文件大?。?/td> 0K
描述： IC DSP CTLR 16BIT 196CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： SPI，SSP
時(shí)鐘速率： 150MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 196-BGA
供應(yīng)商設(shè)備封裝： 196-MBGA（15x15）
包裝： 托盤(pán)
ADSP-21992
Rev. A
|
Page 41 of 60
|
August 2007
Serial Port Timing
Table 23 and Figure 13 describe SPORT transmit and receive
operations, while Figure 14 and Figure 15 describe SPORT
frame sync operations.
Table 23. Serial Port1, 2
Parameter
Min
Max
Unit
External Clock Timing Requirements
tSFSE
TFS/RFS Setup Before TCLK/RCLK3
4ns
tHFSE
TFS/RFS Hold After TCLK/RCLK3
4ns
tSDRE
Receive Data Setup Before RCLK3
1.5
ns
tHDRE
Receive Data Hold After RCLK3
4ns
tSCLKW
TCLK/RCLK Width
0.5tHCLK –1
ns
tSCLK
TCLK/RCLK Period
2tHCLK
ns
Internal Clock Timing Requirements
tSFSI
TFS Setup Before TCLK4; RFS Setup Before RCLK3
4ns
tHFSI
TFS/RFS Hold After TCLK/RCLK3
3ns
tSDRI
Receive Data Setup Before RCLK3
2ns
tHDRI
Receive Data Hold After RCLK3
5ns
External or Internal Clock Switching Characteristics
tDFSE
TFS/RFS Delay After TCLK/RCLK (Internally
Generated FS)4
14
ns
tHOFSE
TFS/RFS Hold After TCLK/RCLK (Internally
Generated FS)4
3ns
External Clock Switching Characteristics
tDDTE
Transmit Data Delay After TCLK4
13.4
ns
tHDTE
Transmit Data Hold After TCLK4
4ns
Internal Clock Switching Characteristics
tDDTI
Transmit Data Delay After TCLK4
13.4
ns
tHDTI
Transmit Data Hold After TCLK4
4ns
tSCLKIW
TCLK/RCLK Width
0.5tHCLK – 3.5
0.5tHCLK + 2.5
ns
Enable and Three-State Switching Characteristics5
tDTENE
Data Enable from External TCLK4
0
12.1
ns
tDDTTE
Data Disable from External TCLK4
13
ns
tDTENI
Data Enable from Internal TCLK4
013
ns
tDDTTI
Data Disable from External TCLK4
12
ns
External Late Frame Sync Switching Characteristics
tDDTLFSE
Data Delay from Late External TFS with MCE =1, MFD =06, 7
10.5
ns
tDTENLFSE
Data Enable from Late FS or MCE =1, MFD =06, 7
3.5
ns
1 To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.
2 Word selected timing for I2S mode is the same as TFS/RFS timing (normal framing only).
3 Referenced to sample edge.
4 Referenced to drive edge.
5 Only applies to SPORT.
6 MCE =1, TFS enable, and TFS valid follow tDDTENFS and tDDTLFSE.
7 If external RFSD/TFS setup to RCLK/TCLK > 0.5tLSCK, tDDTLSCK and tDTENLSCK apply; otherwise, tDDTLFSE and tDTENLFS apply.
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