Timing Requirements: tIFS
參數(shù)資料
型號: ADSP-2181KSZ-160
廠商: Analog Devices Inc
文件頁數(shù): 7/32頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 128-PQFP
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 同步串行端口(SSP)
時(shí)鐘速率: 40MHz
非易失內(nèi)存: 外部
芯片上RAM: 80kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-MQFP(14x20)
包裝: 托盤
ADSP-2181
–15–
REV. D
Parameter
Min
Max
Unit
Interrupts and Flag
Timing Requirements:
tIFS
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
0.25tCK + 15
ns
tIFH
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
0.25tCK
ns
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low
5
0.5tCK – 7
ns
tFOD
Flag Output Delay from CLKOUT Low
5
0.5tCK + 5
ns
NOTES
1If
IRQx and FI inputs meet t
IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
tFOD
tFOH
tIFH
tIFS
CLKOUT
FLAG
OUTPUTS
IRQx
FI
PFx
Figure 9. Interrupts and Flags
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