參數(shù)資料
型號(hào): ADSP-21266
廠商: Analog Devices, Inc.
英文描述: SHARC Embedded Processor
中文描述: SHARC處理器嵌入式處理器
文件頁數(shù): 32/44頁
文件大?。?/td> 426K
代理商: ADSP-21266
Rev. B
|
Page 32 of 44
|
May 2005
ADSP-21266
Input Data Port (IDP)
The timing requirements for the IDP are given in
Table 28
and
Figure 23
. IDP Signals (SCLK, FS, SDATA) are routed to the
DAI_P20
1 pins using the SRU. Therefore, the timing specifi-
cations provided below are valid at the DAI_P20
1 pins.
Table 28. Input Data Port (IDP)
Parameter
Timing Requirements
t
SISFS
t
SIHFS
t
SISD
t
SIHD
t
IDPCLKW
t
IDPCLK
Min
Max
Unit
FS Setup Before SCLK Rising Edge
1
FS Hold After SCLK Rising Edge
1
SData Setup Before SCLK Rising Edge
1
SData Hold After SCLK Rising Edge
1
Clock Width
Clock Period
2.5
2.5
2.5
2.5
7
20
ns
ns
ns
ns
ns
ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either
CLKIN or any of the DAI pins.
Figure 23. Input Data Port (IDP)
DAI_P20
1
(SCLK)
DAI_P20
1
(FS)
SAMPLE EDGE
t
SISD
t
SIHD
t
SISFS
t
SIHFS
t
IDPCLKW
DAI_P20
1
(SDATA)
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