參數(shù)資料
型號: ADSP-21266
廠商: Analog Devices, Inc.
英文描述: SHARC Embedded Processor
中文描述: SHARC處理器嵌入式處理器
文件頁數(shù): 31/44頁
文件大?。?/td> 426K
代理商: ADSP-21266
ADSP-21266
Rev. B
|
Page 31 of 44
|
May 2005
Figure 22. Serial Ports
DRIVE EDGE
DAI_P20–1
SCLK (INT)
DRIVE EDGE
DRIVE EDGE
SCLK
DAI_P20–1
SCLK (EXT)
t
DDTTE
t
DDTEN
t
DDTIN
DAI_P20–1
(DATA CHANNEL A/B)
DAI_P20–1
(DATA CHANNEL A/B)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DRIVE EDGE
SAMPLE EDGE
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
SDRI
t
HDRI
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
t
SDRE
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
DAI_P20–1
(DATA CHANNEL A/B)
t
DDTI
DRIVE EDGE
SAMPLE EDGE
DATA TRANSMIT—INTERNAL CLOCK
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
t
HDTI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DDTE
DRIVE EDGE
SAMPLE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
t
SFSE
t
HFSE
t
DFSE
t
HOFSE
t
SCLKW
t
HDTE
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL A/B)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL A/B)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL A/B)
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