參數(shù)資料
型號(hào): ADSP-21266
廠商: Analog Devices, Inc.
英文描述: SHARC Embedded Processor
中文描述: SHARC處理器嵌入式處理器
文件頁(yè)數(shù): 19/44頁(yè)
文件大小: 426K
代理商: ADSP-21266
ADSP-21266
Rev. B
|
Page 19 of 44
|
May 2005
Clock Input
See
Table 11
and
Figure 7
.
Clock Signals
The ADSP-21266 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21266 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL.
Figure 8
shows
the component connections used for a crystal operating in fun-
damental mode. Note that the 200 MHz clock rate is achieved
using a 12.5 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN).
Table 11. Clock Input
Parameter
150 MHz
Min
200 MHz
Min
Unit
Max
Max
Timing Requirements
t
CK
t
CKL
t
CKH
t
CKRF
t
CCLK
1
Applies only for CLKCFG1
0 = 00 and default values for PLL control bits in PMCTL.
2
Applies only for CLKCFG1
0 = 01 and default values for PLL control bits in PMCTL.
3
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V – 2.0 V)
CCLK Period
3
20
1
7.5
1
7.5
1
160
2
80
2
80
2
3
10
15
1
6
1
6
1
5
160
2
80
2
80
2
3
10
ns
ns
ns
ns
ns
6.66
Figure 7. Clock Input
Figure 8. 150 MHz or 200 MHz Operation with a 12.5 MHz
Fundamental Mode Crystal
CLKIN
t
CK
t
CKH
t
CKL
CLKIN
XTAL
C1
C2
X1
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
1M
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